Stratix-II <==> Virtex4 interconnect; 10 GB Ethernet cores

Has anybody had any showstopping problems when interconnecting
Stratix-II and Virtex4 (EP2S180 & LX200) ? We just want to have a mass
differential interconnect for a source-synchronous interface on
'left-over' pins for future expansion. Have never used Altera before
but I realize the banking is quite different.
Also, any experiences good or bad with 10GB Ethernet MAC cores from
both Xilinx and Altera ?

Thanks, 

-Martin

Why even bother with Ethernet?  Two FPGA's from any vender will talk with
very little troubles.  Do you need speed or distance?

Simon


<martinh@qualcomm.com> wrote in message
news:mfa2t15d98ot783c0i01p5n279nn3t0s4d@4ax.com...
> Has anybody had any showstopping problems when interconnecting
> Stratix-II and Virtex4 (EP2S180 & LX200) ? We just want to have a mass
> differential interconnect for a source-synchronous interface on
> 'left-over' pins for future expansion. Have never used Altera before
> but I realize the banking is quite different.
> Also, any experiences good or bad with 10GB Ethernet MAC cores from
> both Xilinx and Altera ?
>
> Thanks,
>
> -Martin