Hello, I am using ModelSim SE Plus 5.7d. VHDL code compiles and loads fine. However, if I use the "add wave *" command, ModelSim smply quits, regardless of what I put in the "*" field. Invoking it from FpgaAdvantage 6.1 shows me the following: Performing hierarchical generation through components... Checking which design units need saving Incrementally generating HDL... . . . Generation completed successfully. -------------------------------------------------------- Comparing HDL files with compiled files ... Current working directory is C:/FPGAdv61/Hds/bin Executing data preparation plug-in for ModelSim 5.5 - 5.7 Nothing to compile - design is up to date Data preparation step completed, check transcript... --------------------------------------------------------------------------------- Reading C:/FPGAdv61/Modeltech/tcl/vsim/pref.tcl Reading C:/FPGAdv61/Hds/resources/downstream/modelsim/hdsInit.tc_ Connected to HDS # Attempting stack trace sig 11 # Signal caught: signo [11] # vsim_stacktrace.vstf written # Current time Fri Jan 20 19:54:08 2006 # ModelSim Stack Trace # Program = vsim # Id = "5.7d" # Version = "2003.05" # Date = "May 10 2003" # Platform = win32 # 0 0x00511e4f: '<unknown (@0x511e4f)> + 0x6aaef' # 1 0x00511e99: '<unknown (@0x511e99)> + 0x6ab39' # Corrupt Call Stack ** Fatal: (SIGSEGV) Bad pointer access. Closing vsim. ** Fatal: vsim is exiting with code 211. (Exit codes are defined in the ModelSim messages appendix of the ModelSim User's Manual.) How can I solve this? Regards, JaaC
Modelsim problem
Started by ●January 20, 2006
Reply by ●January 21, 20062006-01-21
If you are under maintenance then try a later release (currently 6.1c), alternatively, log a support call with Mentor/Europractice, Hans www.ht-lab.com "Jaime Andr�s Aranguren Cardona" <jaime.aranguren@gmail.com> wrote in message news:1137804897.254287.239800@g14g2000cwa.googlegroups.com...> Hello, > > I am using ModelSim SE Plus 5.7d. VHDL code compiles and loads fine. > However, if I use the "add wave *" command, ModelSim smply quits, > regardless of what I put in the "*" field. > Invoking it from FpgaAdvantage 6.1 shows me the following: > > > Performing hierarchical generation through components... > Checking which design units need saving > Incrementally generating HDL... > > . . . > Generation completed successfully. > -------------------------------------------------------- > Comparing HDL files with compiled files ... > > Current working directory is C:/FPGAdv61/Hds/bin > > Executing data preparation plug-in for ModelSim 5.5 - 5.7 > > Nothing to compile - design is up to date > Data preparation step completed, check transcript... > --------------------------------------------------------------------------------- > Reading C:/FPGAdv61/Modeltech/tcl/vsim/pref.tcl > Reading C:/FPGAdv61/Hds/resources/downstream/modelsim/hdsInit.tc_ > Connected to HDS > # Attempting stack trace sig 11 > # Signal caught: signo [11] > # vsim_stacktrace.vstf written > # Current time Fri Jan 20 19:54:08 2006 > # ModelSim Stack Trace > # Program = vsim > # Id = "5.7d" > # Version = "2003.05" > # Date = "May 10 2003" > # Platform = win32 > # 0 0x00511e4f: '<unknown (@0x511e4f)> + 0x6aaef' > # 1 0x00511e99: '<unknown (@0x511e99)> + 0x6ab39' > > # Corrupt Call Stack > > ** Fatal: (SIGSEGV) Bad pointer access. Closing vsim. > ** Fatal: vsim is exiting with code 211. > (Exit codes are defined in the ModelSim messages appendix > of the ModelSim User's Manual.) > > How can I solve this? > > Regards, > > JaaC >
Reply by ●January 21, 20062006-01-21
On 20 Jan 2006 17:01:12 -0800, "Jaime Andr�s Aranguren Cardona" <jaime.aranguren@gmail.com> wrote:>Hello, > >I am using ModelSim SE Plus 5.7d. VHDL code compiles and loads fine. >However, if I use the "add wave *" command, ModelSim smply quits, >regardless of what I put in the "*" field. >Invoking it from FpgaAdvantage 6.1 shows me the following:>** Fatal: (SIGSEGV) Bad pointer access. Closing vsim. >** Fatal: vsim is exiting with code 211. >(Exit codes are defined in the ModelSim messages appendix >of the ModelSim User's Manual.) > >How can I solve this? >I don't have the answer, but there are a couple of things to try. (1) there may be problems in the interaction between HDS and Modelsim. So try invoking ModelSim standalone, loading the design, and "Add Wave" from its own GUI, and see if the problem persists. (2) I vaguely remember at least one "bad Modelsim" around that era; it may be worth finding out the latest Modelsim you are licensed to run. If you are running it, then try a slightly earlier one... My distributor was very good about helping to the extent they could on an expired ("out of maintenance") licence, it ensured I came back to them when the company had more money! - Brian
Reply by ●January 21, 20062006-01-21
Hi Jaime, Brian made a good point to run your design outside HDL designer. I had a similar problem some time ago and fixed it by un-ticking the "Enable Communication with HDS" tickbox which you find on the start Modelsim dialogue box. I would also suggest to update HDS to 2005.2 if you are not already running that version. Hans. www.ht-lab.com "Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:atk4t1pes94aspjl40ctfuns8mdkgrvvrn@4ax.com...> On 20 Jan 2006 17:01:12 -0800, "Jaime Andr�s Aranguren Cardona" > <jaime.aranguren@gmail.com> wrote: > >>Hello, >> >>I am using ModelSim SE Plus 5.7d. VHDL code compiles and loads fine. >>However, if I use the "add wave *" command, ModelSim smply quits, >>regardless of what I put in the "*" field. >>Invoking it from FpgaAdvantage 6.1 shows me the following: > >>** Fatal: (SIGSEGV) Bad pointer access. Closing vsim. >>** Fatal: vsim is exiting with code 211. >>(Exit codes are defined in the ModelSim messages appendix >>of the ModelSim User's Manual.) >> >>How can I solve this? >> > I don't have the answer, but there are a couple of things to try. > > (1) there may be problems in the interaction between HDS and Modelsim. > So try invoking ModelSim standalone, loading the design, and "Add Wave" > from its own GUI, and see if the problem persists. > > (2) I vaguely remember at least one "bad Modelsim" around that era; it > may be worth finding out the latest Modelsim you are licensed to run. If > you are running it, then try a slightly earlier one... > > My distributor was very good about helping to the extent they could on > an expired ("out of maintenance") licence, it ensured I came back to > them when the company had more money! > > - Brian
Reply by ●January 21, 20062006-01-21
Jaime Andr�s Aranguren Cardona wrote:> Hello, > > I am using ModelSim SE Plus 5.7d. VHDL code compiles and loads fine. > However, if I use the "add wave *" command, ModelSim smply quits, > regardless of what I put in the "*" field. > Invoking it from FpgaAdvantage 6.1 shows me the following: > > ... > # Corrupt Call Stack > > ** Fatal: (SIGSEGV) Bad pointer access. Closing vsim. > ** Fatal: vsim is exiting with code 211. > (Exit codes are defined in the ModelSim messages appendix > of the ModelSim User's Manual.) > > How can I solve this?In my experience, this is almost always caused by *mumble* problems in compiling libraries. Okay, that might be somewhat vague, but I have not figured out exactly what circumstances cause it. One circumstance that causes it is if I move a library, but don't recompile a file (which may be in another library) that uses it. Often, I can find the problem simply by reading the transcript file that Modelsim generates. Somewhere in there, I will usually find a mention of a library that it didn't load, or had a problem with. Another method is to simply recompile all the libraries and files you are using, in the correct order. As a final desperation measure, instead of loading the whole project, load just pieces of it. Eventually you can narrow it down to the piece that is crashing, and work your way backwards to find exactly the file. If it is in a library, just go to the library directory and load pieces of that into Modelsim.
Reply by ●January 22, 20062006-01-22
