Hi there, i`m trying to get a SoC runinng, which is based on a OR1200 soft-processor in an Spartan 3 device. At the moment the system is working (25 MHz, with UART, external SRAM and an SMSC 9118 connected-done with ISE 7.1.04 and 8.1.02). If i`m trying to re-synthesize the whole system with little changes or removed peripherals, the processor seems to get very instable and the execution of the formerly proper working code fails. I`ve also tried to enable the caches for instructions and data, but the result is the same. I guess, the whole system and the processor is very sensitive for timing problems caused by disadvantageous place and route. My questions: Does anyone have experience with implementing OR1200 on spartan 3 ? Is there any reference-desing available, which works with the new debug-interface (i doesnt get it to work) and /or enabled caches ? Any hints for getting better implementation-results (settings of ISE, maybe manually place and route)? any hint would be helpful .. thanks Th. Oehme
OpenRisc 1200 on Spartan 3 - problems with stability and enabling cache
Started by ●February 23, 2006
Reply by ●February 23, 20062006-02-23
Thomas, Thomas Oehme wrote:> Hi there, > i`m trying to get a SoC runinng, which is based on a OR1200 > soft-processor in an Spartan 3 device. > At the moment the system is working (25 MHz, with UART, external SRAM > and an SMSC 9118 connected-done with ISE 7.1.04 and 8.1.02). > If i`m trying to re-synthesize the whole system with little changes or > removed peripherals, the processor seems to get very instable and the > execution of the formerly proper working code fails. > I`ve also tried to enable the caches for instructions and data, but the > result is the same. > I guess, the whole system and the processor is very sensitive for timing > problems caused by disadvantageous place and route.instead of guessing take look to the timing report, do you have any timing constraints? does it fail on timing? by looking into the timing report you can identify the critical path, and you'll be able to judge yourself if is a design isssue (to many levels of logic) or an implementation issue (poor placement) Have fun, Aurash> > My questions: > Does anyone have experience with implementing OR1200 on spartan 3 ? > Is there any reference-desing available, which works with the new > debug-interface (i doesnt get it to work) and /or enabled caches ? > Any hints for getting better implementation-results (settings of ISE, > maybe manually place and route)? > > any hint would be helpful > > .. thanks > > Th. Oehme >
Reply by ●February 23, 20062006-02-23
Aurelian, thanks for your reply. Of corse i did a look to the timing report. I have no timing constraints specified, but i am using a system clock (25 MHz), which is clearly lower than the maximum clock period from the report(36,2 MHz). Aurelian Lazarut schrieb:> > instead of guessing take look to the timing report, do you have any > timing constraints? does it fail on timing? > by looking into the timing report you can identify the critical path, > and you'll be able to judge yourself if is a design isssue (to many > levels of logic) or an implementation issue (poor placement) > > Have fun, > Aurash >
Reply by ●February 23, 20062006-02-23
Thomas, please try to add some constraints, something like 50 Mhz on your clk, to give a good reason to P&R to improve the placement, and to see is something has changed in the erratic behaviour of your system, but I think is very unlikely to be a tool issue (but not imposible) anyway if you can get 50Mhz to place & route at least will tell you that the timing is not marginal for your design. Aurash Thomas Oehme wrote:> Aurelian, > > thanks for your reply. Of corse i did a look to the timing report. I > have no timing constraints specified, but i am using a system clock > (25 MHz), which is clearly lower than the maximum clock period from the > report(36,2 MHz). > > > Aurelian Lazarut schrieb: > >> >> instead of guessing take look to the timing report, do you have any >> timing constraints? does it fail on timing? >> by looking into the timing report you can identify the critical path, >> and you'll be able to judge yourself if is a design isssue (to many >> levels of logic) or an implementation issue (poor placement) >> >> Have fun, >> Aurash >> >
Reply by ●February 24, 20062006-02-24
You can download the rc20x reference design for Celoxicas board. It works with the new debug interface and caches. It run uClinux with net support using SMC91111 lan chip. You can find it in or1k/rc203 directory in the OpenCores CVS. The design is for a Virtex2 but it should work without much modifications in another board Regards Javier Castillo On Thu, 23 Feb 2006 10:21:09 +0100, Thomas Oehme <toehme@gmail.com> wrote:>Hi there, >i`m trying to get a SoC runinng, which is based on a OR1200 >soft-processor in an Spartan 3 device. >At the moment the system is working (25 MHz, with UART, external SRAM >and an SMSC 9118 connected-done with ISE 7.1.04 and 8.1.02). >If i`m trying to re-synthesize the whole system with little changes or >removed peripherals, the processor seems to get very instable and the >execution of the formerly proper working code fails. >I`ve also tried to enable the caches for instructions and data, but the >result is the same. >I guess, the whole system and the processor is very sensitive for timing >problems caused by disadvantageous place and route. > >My questions: >Does anyone have experience with implementing OR1200 on spartan 3 ? >Is there any reference-desing available, which works with the new >debug-interface (i doesnt get it to work) and /or enabled caches ? >Any hints for getting better implementation-results (settings of ISE, >maybe manually place and route)? > >any hint would be helpful > >.. thanks > >Th. Oehme
