On Wed, 30 Jan 2019 18:13:26 +0100, A.P.Richelieu wrote:> Is there any ARM + FPGA CPU Module running linux using any of: > > * NXP i.MX6/7/... > * Texas Instrument Sitara AM335x or better * Microchip SAMA5 * Renesas > RZ/xxx > > It needs to be connected to a low price FPGA, Intel or Xilinx. > > * Zynq or Intel SoC solutions need not apply. > > Other vendors will be difficult to accept. > > ===================== > > The CPU Module needs at least * 128 MB RAM * 128 MB Flash. > Connector will have * 100 Mbps Ethernet * 12 x 10 Mbps SPI channels > (most will be implemented in the FPGA) > * 5 x 921,200 BAUD serial ports (some in FPGA perhaps) > * SD-Card * A few custom protocol LVDS channels ===================== > The processor has to be connected to an FPGA on a suitable interface > providing 5-10 MB/second transfer rate. > The FPGA needs to have 80-100 free I/O, not including the interface to > the CPU to implement SPIs, UARTs and other custom signals > ===================== > The CPU should be able to load the FPGA after reset. > Preferably right after loading the U-Boot (during the BOOTDELAY timer). > ===================== > Preferably, the processor should be able to access the internals of the > FPGA like it was on the memory bus. > > Putting the FPGA on a 16 bit memory interface will work > > Some chip support a transparent mode where you do a memory read/write > which gets translated to a Quad SPI access, or a NAND flash controller > access. > > I.E: > You can write to a register over SPI by: > FPGA_REGISTER = value; > instead of > > spi_packet = { > .cmd = SPI_WRITE, .addr = FPGA_REGISTER, > .size = sizeof(value), > .data = &value > } > spi_transfer(&spi_packet); > > > We plan to use Yocto for developing Linux, so any Yocto solution would > be appreciated. > > Looking forward to ideas. > > APGoggle cpu module with fpga you will get lots of hits A couple that might work http://www.myirtech.com/list.asp?id=583 https://www.embeddedarm.com/products/TS-4740 -- Chisolm Republic of Texas
ARM + FPGA CPU Module running Yocto Linux?
Started by ●January 30, 2019
Reply by ●January 30, 20192019-01-30
Reply by ●January 30, 20192019-01-30
Den 2019-01-30 kl. 20:18, skrev Joe Chisolm:> On Wed, 30 Jan 2019 18:13:26 +0100, A.P.Richelieu wrote: > >> Is there any ARM + FPGA CPU Module running linux using any of: >> >> * NXP i.MX6/7/... >> * Texas Instrument Sitara AM335x or better * Microchip SAMA5 * Renesas >> RZ/xxx >> >> It needs to be connected to a low price FPGA, Intel or Xilinx. >> >> * Zynq or Intel SoC solutions need not apply. >> >> Other vendors will be difficult to accept. >> >> ===================== >> >> The CPU Module needs at least * 128 MB RAM * 128 MB Flash. >> Connector will have * 100 Mbps Ethernet * 12 x 10 Mbps SPI channels >> (most will be implemented in the FPGA) >> * 5 x 921,200 BAUD serial ports (some in FPGA perhaps) >> * SD-Card * A few custom protocol LVDS channels ===================== >> The processor has to be connected to an FPGA on a suitable interface >> providing 5-10 MB/second transfer rate. >> The FPGA needs to have 80-100 free I/O, not including the interface to >> the CPU to implement SPIs, UARTs and other custom signals >> ===================== >> The CPU should be able to load the FPGA after reset. >> Preferably right after loading the U-Boot (during the BOOTDELAY timer). >> ===================== >> Preferably, the processor should be able to access the internals of the >> FPGA like it was on the memory bus. >> >> Putting the FPGA on a 16 bit memory interface will work >> >> Some chip support a transparent mode where you do a memory read/write >> which gets translated to a Quad SPI access, or a NAND flash controller >> access. >> >> I.E: >> You can write to a register over SPI by: >> FPGA_REGISTER = value; >> instead of >> >> spi_packet = { >> .cmd = SPI_WRITE, .addr = FPGA_REGISTER, >> .size = sizeof(value), >> .data = &value >> } >> spi_transfer(&spi_packet); >> >> >> We plan to use Yocto for developing Linux, so any Yocto solution would >> be appreciated. >> >> Looking forward to ideas. >> >> AP > > Goggle cpu module with fpga > you will get lots of hits > > A couple that might work > http://www.myirtech.com/list.asp?id=583 > https://www.embeddedarm.com/products/TS-4740 > > > > >Thanks, but the myirtech uses the Zync, and the TS-4740 uses a Marvell CPU. This might work: http://teso.rs/arm-fpga-platforms.php NXP ARM Cortex-A5 with Cortex-M controllers and an 80 MHz memory bus to an Artix-7 The AM335x CPU on the Beagleon with an FPGA on a module would be better, since that is a preferred chip. AP
Reply by ●January 30, 20192019-01-30
onsdag den 30. januar 2019 kl. 19.28.43 UTC+1 skrev A.P.Richelieu:> Den 2019-01-30 kl. 18:28, skrev gnuarm.deletethisbit@gmail.com: > > On Wednesday, January 30, 2019 at 12:13:34 PM UTC-5, A.P.Richelieu wrote: > >> Is there any ARM + FPGA CPU Module running linux using any of: > >> > >> * NXP i.MX6/7/... > >> * Texas Instrument Sitara AM335x or better > >> * Microchip SAMA5 > >> * Renesas RZ/xxx > >> > >> It needs to be connected to a low price FPGA, Intel or Xilinx. > >> > >> * Zynq or Intel SoC solutions need not apply. > >> > >> Other vendors will be difficult to accept. > >> > >> ===================== > >> > >> The CPU Module needs at least > >> * 128 MB RAM > >> * 128 MB Flash. > >> Connector will have > >> * 100 Mbps Ethernet > >> * 12 x 10 Mbps SPI channels (most will be implemented in the FPGA) > >> * 5 x 921,200 BAUD serial ports (some in FPGA perhaps) > >> * SD-Card > >> * A few custom protocol LVDS channels > >> ===================== > >> The processor has to be connected to an FPGA on a suitable > >> interface providing 5-10 MB/second transfer rate. > >> The FPGA needs to have 80-100 free I/O, not including the > >> interface to the CPU to implement SPIs, UARTs and other custom signals > >> ===================== > >> The CPU should be able to load the FPGA after reset. > >> Preferably right after loading the U-Boot (during the BOOTDELAY timer). > >> ===================== > >> Preferably, the processor should be able to access the internals > >> of the FPGA like it was on the memory bus. > >> > >> Putting the FPGA on a 16 bit memory interface will work > >> > >> Some chip support a transparent mode where you do a memory read/write > >> which gets translated to a Quad SPI access, or a NAND flash controller > >> access. > >> > >> I.E: > >> You can write to a register over SPI by: > >> FPGA_REGISTER = value; > >> instead of > >> > >> spi_packet = { > >> .cmd = SPI_WRITE, > >> .addr = FPGA_REGISTER, > >> .size = sizeof(value), > >> .data = &value > >> } > >> spi_transfer(&spi_packet); > >> > >> > >> We plan to use Yocto for developing Linux, so any Yocto solution > >> would be appreciated. > >> > >> Looking forward to ideas. > >> > >> AP > > > > I am not familiar with modules (i.e. boards) that contain an ARM and an FPGA unless they are in the same devices which you have an unstated reason to avoid. Care you share the rational for not using those obvious solutions? > > > > You don't indicate what your outline size requirements are. Would you consider a daughter board mounted on something like a Beagle board? What sort of quantities would you be expecting to buy? > > > > We will do a base board, for which we need a CPU+FPGA module, so no > adding two boards together. > > We are looking for an existing board for some prototyping. > Not having someone design it for us. A few boards will be OK. >if you only need a few for prototyping why does it matter if it is stacked boards?
Reply by ●January 30, 20192019-01-30
Den 2019-01-30 kl. 19:53, skrev Gerhard Hoffmann:> Am 30.01.19 um 19:21 schrieb A.P.Richelieu: >> Den 2019-01-30 kl. 18:44, skrev lasselangwadtchristensen@gmail.com: >>> onsdag den 30. januar 2019 kl. 18.13.34 UTC+1 skrev A.P.Richelieu: >>>> Is there any ARM + FPGA CPU Module running linux using any of: >>>> >>>> * NXP i.MX6/7/... >>>> * Texas Instrument Sitara AM335x or better >>>> * Microchip SAMA5 >>>> * Renesas RZ/xxx >>>> >>>> It needs to be connected to a low price FPGA, Intel or Xilinx. >>>> >>>> * Zynq or Intel SoC solutions need not apply. >>>> >>>> Other vendors will be difficult to accept. >>>> >>>> ===================== >>>> >>>> The CPU Module needs at least >>>> * 128 MB RAM >>>> * 128 MB Flash. >>>> Connector will have >>>> * 100 Mbps Ethernet >>>> * 12 x 10 Mbps SPI channels (most will be implemented in the FPGA) >>>> * 5 x 921,200 BAUD serial ports (some in FPGA perhaps) >>>> * SD-Card >>>> * A few custom protocol LVDS channels >>>> ===================== >>>> The processor has to be connected to an FPGA on a suitable >>>> interface providing 5-10 MB/second transfer rate. >>>> The FPGA needs to have 80-100 free I/O, not including the >>>> interface to the CPU to implement SPIs, UARTs and other custom signals >>>> ===================== >>>> The CPU should be able to load the FPGA after reset. >>>> Preferably right after loading the U-Boot (during the BOOTDELAY timer). >>>> ===================== >>>> Preferably, the processor should be able to access the internals >>>> of the FPGA like it was on the memory bus. >>>> >>>> Putting the FPGA on a 16 bit memory interface will work >>>> > > The BeagleBoneBlack has at least a 16 bit multiplexed data bus, even > when it shares pins with other stuff. >There is also the integrated solution from Octavo Systems. Beaglebone with eMMC and DDR3 SDRAM + Power in a 400 pin BGA. Adding an FPGA to that, with a high speed bus: Yum, Yum... AP> I'm looking into that because I want a FPGA that has support > for some JESDI204B lanes to connect to some contemporary ADCs and DACs. > > And on-chip CPUs have been a royal pain from Power-PC to Picoblaze. > I like it when I know that at least my Linux runs stable, so bugs > must be in user land or the hardware - and not in my driver that > kills my ssh access. > > It found it quite OK to run the time-critical stuff on a PRU and > just hand the Linux-ARM the time-decoupled data via shared buffers. > There is a C compiler for the PRUs in the standard BBB Linux distribution. > > regards, > Gerhard
Reply by ●January 30, 20192019-01-30
Den 2019-01-30 kl. 20:27, skrev lasselangwadtchristensen@gmail.com:> onsdag den 30. januar 2019 kl. 19.28.43 UTC+1 skrev A.P.Richelieu: >> Den 2019-01-30 kl. 18:28, skrev gnuarm.deletethisbit@gmail.com: >>> On Wednesday, January 30, 2019 at 12:13:34 PM UTC-5, A.P.Richelieu wrote: >>>> Is there any ARM + FPGA CPU Module running linux using any of: >>>> >>>> * NXP i.MX6/7/... >>>> * Texas Instrument Sitara AM335x or better >>>> * Microchip SAMA5 >>>> * Renesas RZ/xxx >>>> >>>> It needs to be connected to a low price FPGA, Intel or Xilinx. >>>> >>>> * Zynq or Intel SoC solutions need not apply. >>>> >>>> Other vendors will be difficult to accept. >>>> >>>> ===================== >>>> >>>> The CPU Module needs at least >>>> * 128 MB RAM >>>> * 128 MB Flash. >>>> Connector will have >>>> * 100 Mbps Ethernet >>>> * 12 x 10 Mbps SPI channels (most will be implemented in the FPGA) >>>> * 5 x 921,200 BAUD serial ports (some in FPGA perhaps) >>>> * SD-Card >>>> * A few custom protocol LVDS channels >>>> ===================== >>>> The processor has to be connected to an FPGA on a suitable >>>> interface providing 5-10 MB/second transfer rate. >>>> The FPGA needs to have 80-100 free I/O, not including the >>>> interface to the CPU to implement SPIs, UARTs and other custom signals >>>> ===================== >>>> The CPU should be able to load the FPGA after reset. >>>> Preferably right after loading the U-Boot (during the BOOTDELAY timer). >>>> ===================== >>>> Preferably, the processor should be able to access the internals >>>> of the FPGA like it was on the memory bus. >>>> >>>> Putting the FPGA on a 16 bit memory interface will work >>>> >>>> Some chip support a transparent mode where you do a memory read/write >>>> which gets translated to a Quad SPI access, or a NAND flash controller >>>> access. >>>> >>>> I.E: >>>> You can write to a register over SPI by: >>>> FPGA_REGISTER = value; >>>> instead of >>>> >>>> spi_packet = { >>>> .cmd = SPI_WRITE, >>>> .addr = FPGA_REGISTER, >>>> .size = sizeof(value), >>>> .data = &value >>>> } >>>> spi_transfer(&spi_packet); >>>> >>>> >>>> We plan to use Yocto for developing Linux, so any Yocto solution >>>> would be appreciated. >>>> >>>> Looking forward to ideas. >>>> >>>> AP >>> >>> I am not familiar with modules (i.e. boards) that contain an ARM and an FPGA unless they are in the same devices which you have an unstated reason to avoid. Care you share the rational for not using those obvious solutions? >>> >>> You don't indicate what your outline size requirements are. Would you consider a daughter board mounted on something like a Beagle board? What sort of quantities would you be expecting to buy? >>> >> >> We will do a base board, for which we need a CPU+FPGA module, so no >> adding two boards together. >> >> We are looking for an existing board for some prototyping. >> Not having someone design it for us. A few boards will be OK. >> > > if you only need a few for prototyping why does it matter if it > is stacked boards? >It will be mounted on a low volume test board, to test the functionality outside the module. There is a maximum height restriction. The real motherboard can have a different module connector. AP
Reply by ●January 30, 20192019-01-30
onsdag den 30. januar 2019 kl. 20.35.51 UTC+1 skrev A.P.Richelieu:> Den 2019-01-30 kl. 20:27, skrev lasselangwadtchristensen@gmail.com: > > onsdag den 30. januar 2019 kl. 19.28.43 UTC+1 skrev A.P.Richelieu: > >> Den 2019-01-30 kl. 18:28, skrev gnuarm.deletethisbit@gmail.com: > >>> On Wednesday, January 30, 2019 at 12:13:34 PM UTC-5, A.P.Richelieu wrote: > >>>> Is there any ARM + FPGA CPU Module running linux using any of: > >>>> > >>>> * NXP i.MX6/7/... > >>>> * Texas Instrument Sitara AM335x or better > >>>> * Microchip SAMA5 > >>>> * Renesas RZ/xxx > >>>> > >>>> It needs to be connected to a low price FPGA, Intel or Xilinx. > >>>> > >>>> * Zynq or Intel SoC solutions need not apply. > >>>> > >>>> Other vendors will be difficult to accept. > >>>> > >>>> ===================== > >>>> > >>>> The CPU Module needs at least > >>>> * 128 MB RAM > >>>> * 128 MB Flash. > >>>> Connector will have > >>>> * 100 Mbps Ethernet > >>>> * 12 x 10 Mbps SPI channels (most will be implemented in the FPGA) > >>>> * 5 x 921,200 BAUD serial ports (some in FPGA perhaps) > >>>> * SD-Card > >>>> * A few custom protocol LVDS channels > >>>> ===================== > >>>> The processor has to be connected to an FPGA on a suitable > >>>> interface providing 5-10 MB/second transfer rate. > >>>> The FPGA needs to have 80-100 free I/O, not including the > >>>> interface to the CPU to implement SPIs, UARTs and other custom signals > >>>> ===================== > >>>> The CPU should be able to load the FPGA after reset. > >>>> Preferably right after loading the U-Boot (during the BOOTDELAY timer). > >>>> ===================== > >>>> Preferably, the processor should be able to access the internals > >>>> of the FPGA like it was on the memory bus. > >>>> > >>>> Putting the FPGA on a 16 bit memory interface will work > >>>> > >>>> Some chip support a transparent mode where you do a memory read/write > >>>> which gets translated to a Quad SPI access, or a NAND flash controller > >>>> access. > >>>> > >>>> I.E: > >>>> You can write to a register over SPI by: > >>>> FPGA_REGISTER = value; > >>>> instead of > >>>> > >>>> spi_packet = { > >>>> .cmd = SPI_WRITE, > >>>> .addr = FPGA_REGISTER, > >>>> .size = sizeof(value), > >>>> .data = &value > >>>> } > >>>> spi_transfer(&spi_packet); > >>>> > >>>> > >>>> We plan to use Yocto for developing Linux, so any Yocto solution > >>>> would be appreciated. > >>>> > >>>> Looking forward to ideas. > >>>> > >>>> AP > >>> > >>> I am not familiar with modules (i.e. boards) that contain an ARM and an FPGA unless they are in the same devices which you have an unstated reason to avoid. Care you share the rational for not using those obvious solutions? > >>> > >>> You don't indicate what your outline size requirements are. Would you consider a daughter board mounted on something like a Beagle board? What sort of quantities would you be expecting to buy? > >>> > >> > >> We will do a base board, for which we need a CPU+FPGA module, so no > >> adding two boards together. > >> > >> We are looking for an existing board for some prototyping. > >> Not having someone design it for us. A few boards will be OK. > >> > > > > if you only need a few for prototyping why does it matter if it > > is stacked boards? > > > > It will be mounted on a low volume test board, to test the functionality > outside the module. There is a maximum height restriction. > The real motherboard can have a different module connector.if you are doing a board anyway just put the FPGA on that
Reply by ●January 30, 20192019-01-30
Den 2019-01-30 kl. 21:05, skrev lasselangwadtchristensen@gmail.com:> onsdag den 30. januar 2019 kl. 20.35.51 UTC+1 skrev A.P.Richelieu: >> Den 2019-01-30 kl. 20:27, skrev lasselangwadtchristensen@gmail.com: >>> onsdag den 30. januar 2019 kl. 19.28.43 UTC+1 skrev A.P.Richelieu: >>>> Den 2019-01-30 kl. 18:28, skrev gnuarm.deletethisbit@gmail.com: >>>>> On Wednesday, January 30, 2019 at 12:13:34 PM UTC-5, A.P.Richelieu wrote: >>>>>> Is there any ARM + FPGA CPU Module running linux using any of: >>>>>> >>>>>> * NXP i.MX6/7/... >>>>>> * Texas Instrument Sitara AM335x or better >>>>>> * Microchip SAMA5 >>>>>> * Renesas RZ/xxx >>>>>> >>>>>> It needs to be connected to a low price FPGA, Intel or Xilinx. >>>>>> >>>>>> * Zynq or Intel SoC solutions need not apply. >>>>>> >>>>>> Other vendors will be difficult to accept. >>>>>> >>>>>> ===================== >>>>>> >>>>>> The CPU Module needs at least >>>>>> * 128 MB RAM >>>>>> * 128 MB Flash. >>>>>> Connector will have >>>>>> * 100 Mbps Ethernet >>>>>> * 12 x 10 Mbps SPI channels (most will be implemented in the FPGA) >>>>>> * 5 x 921,200 BAUD serial ports (some in FPGA perhaps) >>>>>> * SD-Card >>>>>> * A few custom protocol LVDS channels >>>>>> ===================== >>>>>> The processor has to be connected to an FPGA on a suitable >>>>>> interface providing 5-10 MB/second transfer rate. >>>>>> The FPGA needs to have 80-100 free I/O, not including the >>>>>> interface to the CPU to implement SPIs, UARTs and other custom signals >>>>>> ===================== >>>>>> The CPU should be able to load the FPGA after reset. >>>>>> Preferably right after loading the U-Boot (during the BOOTDELAY timer). >>>>>> ===================== >>>>>> Preferably, the processor should be able to access the internals >>>>>> of the FPGA like it was on the memory bus. >>>>>> >>>>>> Putting the FPGA on a 16 bit memory interface will work >>>>>> >>>>>> Some chip support a transparent mode where you do a memory read/write >>>>>> which gets translated to a Quad SPI access, or a NAND flash controller >>>>>> access. >>>>>> >>>>>> I.E: >>>>>> You can write to a register over SPI by: >>>>>> FPGA_REGISTER = value; >>>>>> instead of >>>>>> >>>>>> spi_packet = { >>>>>> .cmd = SPI_WRITE, >>>>>> .addr = FPGA_REGISTER, >>>>>> .size = sizeof(value), >>>>>> .data = &value >>>>>> } >>>>>> spi_transfer(&spi_packet); >>>>>> >>>>>> >>>>>> We plan to use Yocto for developing Linux, so any Yocto solution >>>>>> would be appreciated. >>>>>> >>>>>> Looking forward to ideas. >>>>>> >>>>>> AP >>>>> >>>>> I am not familiar with modules (i.e. boards) that contain an ARM and an FPGA unless they are in the same devices which you have an unstated reason to avoid. Care you share the rational for not using those obvious solutions? >>>>> >>>>> You don't indicate what your outline size requirements are. Would you consider a daughter board mounted on something like a Beagle board? What sort of quantities would you be expecting to buy? >>>>> >>>> >>>> We will do a base board, for which we need a CPU+FPGA module, so no >>>> adding two boards together. >>>> >>>> We are looking for an existing board for some prototyping. >>>> Not having someone design it for us. A few boards will be OK. >>>> >>> >>> if you only need a few for prototyping why does it matter if it >>> is stacked boards? >>> >> >> It will be mounted on a low volume test board, to test the functionality >> outside the module. There is a maximum height restriction. >> The real motherboard can have a different module connector. > > if you are doing a board anyway just put the FPGA on that >Not going to happen. Please everyone. I know what I plan to do and I am not going to explain why. I want a CPU module. That CPU module has those restrictions I have mentioned. That means * no Zync * No SoC * no FPGA outside the module * no CPU outside the module * Not two PCBs * No Marvell CPU, No CPU which is not delivered by NXP,TI, or MicroChip. * No SPI interface between CPU and FPGA. * Not anything that will deviate from what I described so far. AP
Reply by ●January 30, 20192019-01-30
onsdag den 30. januar 2019 kl. 21.33.14 UTC+1 skrev A.P.Richelieu:> Den 2019-01-30 kl. 21:05, skrev lasselangwadtchristensen@gmail.com: > > onsdag den 30. januar 2019 kl. 20.35.51 UTC+1 skrev A.P.Richelieu: > >> Den 2019-01-30 kl. 20:27, skrev lasselangwadtchristensen@gmail.com: > >>> onsdag den 30. januar 2019 kl. 19.28.43 UTC+1 skrev A.P.Richelieu: > >>>> Den 2019-01-30 kl. 18:28, skrev gnuarm.deletethisbit@gmail.com: > >>>>> On Wednesday, January 30, 2019 at 12:13:34 PM UTC-5, A.P.Richelieu wrote: > >>>>>> Is there any ARM + FPGA CPU Module running linux using any of: > >>>>>> > >>>>>> * NXP i.MX6/7/... > >>>>>> * Texas Instrument Sitara AM335x or better > >>>>>> * Microchip SAMA5 > >>>>>> * Renesas RZ/xxx > >>>>>> > >>>>>> It needs to be connected to a low price FPGA, Intel or Xilinx. > >>>>>> > >>>>>> * Zynq or Intel SoC solutions need not apply. > >>>>>> > >>>>>> Other vendors will be difficult to accept. > >>>>>> > >>>>>> ===================== > >>>>>> > >>>>>> The CPU Module needs at least > >>>>>> * 128 MB RAM > >>>>>> * 128 MB Flash. > >>>>>> Connector will have > >>>>>> * 100 Mbps Ethernet > >>>>>> * 12 x 10 Mbps SPI channels (most will be implemented in the FPGA) > >>>>>> * 5 x 921,200 BAUD serial ports (some in FPGA perhaps) > >>>>>> * SD-Card > >>>>>> * A few custom protocol LVDS channels > >>>>>> ===================== > >>>>>> The processor has to be connected to an FPGA on a suitable > >>>>>> interface providing 5-10 MB/second transfer rate. > >>>>>> The FPGA needs to have 80-100 free I/O, not including the > >>>>>> interface to the CPU to implement SPIs, UARTs and other custom signals > >>>>>> ===================== > >>>>>> The CPU should be able to load the FPGA after reset. > >>>>>> Preferably right after loading the U-Boot (during the BOOTDELAY timer). > >>>>>> ===================== > >>>>>> Preferably, the processor should be able to access the internals > >>>>>> of the FPGA like it was on the memory bus. > >>>>>> > >>>>>> Putting the FPGA on a 16 bit memory interface will work > >>>>>> > >>>>>> Some chip support a transparent mode where you do a memory read/write > >>>>>> which gets translated to a Quad SPI access, or a NAND flash controller > >>>>>> access. > >>>>>> > >>>>>> I.E: > >>>>>> You can write to a register over SPI by: > >>>>>> FPGA_REGISTER = value; > >>>>>> instead of > >>>>>> > >>>>>> spi_packet = { > >>>>>> .cmd = SPI_WRITE, > >>>>>> .addr = FPGA_REGISTER, > >>>>>> .size = sizeof(value), > >>>>>> .data = &value > >>>>>> } > >>>>>> spi_transfer(&spi_packet); > >>>>>> > >>>>>> > >>>>>> We plan to use Yocto for developing Linux, so any Yocto solution > >>>>>> would be appreciated. > >>>>>> > >>>>>> Looking forward to ideas. > >>>>>> > >>>>>> AP > >>>>> > >>>>> I am not familiar with modules (i.e. boards) that contain an ARM and an FPGA unless they are in the same devices which you have an unstated reason to avoid. Care you share the rational for not using those obvious solutions? > >>>>> > >>>>> You don't indicate what your outline size requirements are. Would you consider a daughter board mounted on something like a Beagle board? What sort of quantities would you be expecting to buy? > >>>>> > >>>> > >>>> We will do a base board, for which we need a CPU+FPGA module, so no > >>>> adding two boards together. > >>>> > >>>> We are looking for an existing board for some prototyping. > >>>> Not having someone design it for us. A few boards will be OK. > >>>> > >>> > >>> if you only need a few for prototyping why does it matter if it > >>> is stacked boards? > >>> > >> > >> It will be mounted on a low volume test board, to test the functionality > >> outside the module. There is a maximum height restriction. > >> The real motherboard can have a different module connector. > > > > if you are doing a board anyway just put the FPGA on that > > > > Not going to happen. > > Please everyone. > I know what I plan to do and I am not going to explain why.so you are firmly committed to a plan that involves a board you can't find and might not even exist best of luck
Reply by ●January 30, 20192019-01-30
On Wed, 30 Jan 2019 20:27:03 +0100, A.P.Richelieu wrote:> Den 2019-01-30 kl. 20:18, skrev Joe Chisolm: >> On Wed, 30 Jan 2019 18:13:26 +0100, A.P.Richelieu wrote: >> >>> Is there any ARM + FPGA CPU Module running linux using any of: >>> >>> * NXP i.MX6/7/... >>> * Texas Instrument Sitara AM335x or better * Microchip SAMA5 * Renesas >>> RZ/xxx >>> >>> It needs to be connected to a low price FPGA, Intel or Xilinx. >>> >>> * Zynq or Intel SoC solutions need not apply. >>> >>> Other vendors will be difficult to accept. >>> >>> ===================== >>> >>> The CPU Module needs at least * 128 MB RAM * 128 MB Flash. >>> Connector will have * 100 Mbps Ethernet * 12 x 10 Mbps SPI channels >>> (most will be implemented in the FPGA) >>> * 5 x 921,200 BAUD serial ports (some in FPGA perhaps) >>> * SD-Card * A few custom protocol LVDS channels ===================== >>> The processor has to be connected to an FPGA on a suitable interface >>> providing 5-10 MB/second transfer rate. >>> The FPGA needs to have 80-100 free I/O, not including the interface to >>> the CPU to implement SPIs, UARTs and other custom signals >>> ===================== >>> The CPU should be able to load the FPGA after reset. >>> Preferably right after loading the U-Boot (during the BOOTDELAY >>> timer). >>> ===================== >>> Preferably, the processor should be able to access the internals of >>> the FPGA like it was on the memory bus. >>> >>> Putting the FPGA on a 16 bit memory interface will work >>> >>> Some chip support a transparent mode where you do a memory read/write >>> which gets translated to a Quad SPI access, or a NAND flash controller >>> access. >>> >>> I.E: >>> You can write to a register over SPI by: >>> FPGA_REGISTER = value; >>> instead of >>> >>> spi_packet = { >>> .cmd = SPI_WRITE, .addr = FPGA_REGISTER, >>> .size = sizeof(value), >>> .data = &value >>> } >>> spi_transfer(&spi_packet); >>> >>> >>> We plan to use Yocto for developing Linux, so any Yocto solution would >>> be appreciated. >>> >>> Looking forward to ideas. >>> >>> AP >> >> Goggle cpu module with fpga you will get lots of hits >> >> A couple that might work http://www.myirtech.com/list.asp?id=583 >> https://www.embeddedarm.com/products/TS-4740 >> >> >> >> >> > Thanks, but the myirtech uses the Zync, and the TS-4740 uses a Marvell > CPU. > > This might work: > http://teso.rs/arm-fpga-platforms.php > > NXP ARM Cortex-A5 with Cortex-M controllers and an 80 MHz memory bus to > an Artix-7It will be interesting to see what they think "low cost" is. Please post back here if you get a price from them.> > The AM335x CPU on the Beagleon with an FPGA on a module would be better, > since that is a preferred chip. > > AP-- Chisolm Republic of Texas
Reply by ●January 30, 20192019-01-30
Den 2019-01-30 kl. 22:31, skrev lasselangwadtchristensen@gmail.com:> onsdag den 30. januar 2019 kl. 21.33.14 UTC+1 skrev A.P.Richelieu: >> Den 2019-01-30 kl. 21:05, skrev lasselangwadtchristensen@gmail.com: >>> onsdag den 30. januar 2019 kl. 20.35.51 UTC+1 skrev A.P.Richelieu: >>>> Den 2019-01-30 kl. 20:27, skrev lasselangwadtchristensen@gmail.com: >>>>> onsdag den 30. januar 2019 kl. 19.28.43 UTC+1 skrev A.P.Richelieu: >>>>>> Den 2019-01-30 kl. 18:28, skrev gnuarm.deletethisbit@gmail.com: >>>>>>> On Wednesday, January 30, 2019 at 12:13:34 PM UTC-5, A.P.Richelieu wrote: >>>>>>>> Is there any ARM + FPGA CPU Module running linux using any of: >>>>>>>> >>>>>>>> * NXP i.MX6/7/... >>>>>>>> * Texas Instrument Sitara AM335x or better >>>>>>>> * Microchip SAMA5 >>>>>>>> * Renesas RZ/xxx >>>>>>>> >>>>>>>> It needs to be connected to a low price FPGA, Intel or Xilinx. >>>>>>>> >>>>>>>> * Zynq or Intel SoC solutions need not apply. >>>>>>>> >>>>>>>> Other vendors will be difficult to accept. >>>>>>>> >>>>>>>> ===================== >>>>>>>> >>>>>>>> The CPU Module needs at least >>>>>>>> * 128 MB RAM >>>>>>>> * 128 MB Flash. >>>>>>>> Connector will have >>>>>>>> * 100 Mbps Ethernet >>>>>>>> * 12 x 10 Mbps SPI channels (most will be implemented in the FPGA) >>>>>>>> * 5 x 921,200 BAUD serial ports (some in FPGA perhaps) >>>>>>>> * SD-Card >>>>>>>> * A few custom protocol LVDS channels >>>>>>>> ===================== >>>>>>>> The processor has to be connected to an FPGA on a suitable >>>>>>>> interface providing 5-10 MB/second transfer rate. >>>>>>>> The FPGA needs to have 80-100 free I/O, not including the >>>>>>>> interface to the CPU to implement SPIs, UARTs and other custom signals >>>>>>>> ===================== >>>>>>>> The CPU should be able to load the FPGA after reset. >>>>>>>> Preferably right after loading the U-Boot (during the BOOTDELAY timer). >>>>>>>> ===================== >>>>>>>> Preferably, the processor should be able to access the internals >>>>>>>> of the FPGA like it was on the memory bus. >>>>>>>> >>>>>>>> Putting the FPGA on a 16 bit memory interface will work >>>>>>>> >>>>>>>> Some chip support a transparent mode where you do a memory read/write >>>>>>>> which gets translated to a Quad SPI access, or a NAND flash controller >>>>>>>> access. >>>>>>>> >>>>>>>> I.E: >>>>>>>> You can write to a register over SPI by: >>>>>>>> FPGA_REGISTER = value; >>>>>>>> instead of >>>>>>>> >>>>>>>> spi_packet = { >>>>>>>> .cmd = SPI_WRITE, >>>>>>>> .addr = FPGA_REGISTER, >>>>>>>> .size = sizeof(value), >>>>>>>> .data = &value >>>>>>>> } >>>>>>>> spi_transfer(&spi_packet); >>>>>>>> >>>>>>>> >>>>>>>> We plan to use Yocto for developing Linux, so any Yocto solution >>>>>>>> would be appreciated. >>>>>>>> >>>>>>>> Looking forward to ideas. >>>>>>>> >>>>>>>> AP >>>>>>> >>>>>>> I am not familiar with modules (i.e. boards) that contain an ARM and an FPGA unless they are in the same devices which you have an unstated reason to avoid. Care you share the rational for not using those obvious solutions? >>>>>>> >>>>>>> You don't indicate what your outline size requirements are. Would you consider a daughter board mounted on something like a Beagle board? What sort of quantities would you be expecting to buy? >>>>>>> >>>>>> >>>>>> We will do a base board, for which we need a CPU+FPGA module, so no >>>>>> adding two boards together. >>>>>> >>>>>> We are looking for an existing board for some prototyping. >>>>>> Not having someone design it for us. A few boards will be OK. >>>>>> >>>>> >>>>> if you only need a few for prototyping why does it matter if it >>>>> is stacked boards? >>>>> >>>> >>>> It will be mounted on a low volume test board, to test the functionality >>>> outside the module. There is a maximum height restriction. >>>> The real motherboard can have a different module connector. >>> >>> if you are doing a board anyway just put the FPGA on that >>> >> >> Not going to happen. >> >> Please everyone. >> I know what I plan to do and I am not going to explain why. > > so you are firmly committed to a plan that involves a board you can't > find and might not even existIf we cannot find the module, then we will design it ourselves. Right now, I prefer getting something which is as close to our final solution as possible, but fits from a physical point of view. AP> > best of luck >
