why use an FPGA when a CPLD will do ??

Hey guys/gals

What are the advantages and disadvantages of using a CPLD instead of using 
an FPGA for a design?

Thanks

Matt,

If you use a a cpld, you need to post in comp.arch.cpld

Austin

Matt Clement wrote:

> Hey guys/gals
> 
> What are the advantages and disadvantages of using a CPLD instead of using 
> an FPGA for a design?
> 
> Thanks
> 
> 

"Matt Clement" <clement@nanotechsys.com> wrote in message
news:Qp1Of.111$eP4.86@trnddc05...
> Hey guys/gals
>
> What are the advantages and disadvantages of using a CPLD instead of using
> an FPGA for a design?
>
> Thanks
>
>

lower cost, less power consumption, smaller size, easier configuration

There is a big difference in logic capabilities. Let's express that in
the number of flip-flops or registers:

CPLDs are good for up to 200 flip-flops, they get disproportionally
expensive for larger designs.
Modern FPGAs start at 2,000 flip-flops, and go up to to 200,000
flip-flops, plus many other circuits, like RAM, multipliers etc.

CoolRunner CPLDs offer extremely low power consumption, and small
physical size, and low cost for the smallest parts.
FPGAs fit a much wider range of applications.

The choice between the two technologies is usually quite clear-cut.
Peter Alfke, Xilinx Applications
=====================================
Matt Clement wrote:
> Hey guys/gals
>
> What are the advantages and disadvantages of using a CPLD instead of using
> an FPGA for a design?
> 
> Thanks

There is also the issue that FPGA's configuration data is stored in external
FLASH where as CPLD's are programmed.
It is actually quite easy to reprogram a FPGA on the fly and field update
the external memory while the FPGA is still running.  No special hardware or
algorithms are required.  Downloading a CPLD is usually done from a PC via a
JTAG cable or via a External Chip Programmer.

Simon


"Peter Alfke" <peter@xilinx.com> wrote in message
news:1141424214.234508.233260@p10g2000cwp.googlegroups.com...
> There is a big difference in logic capabilities. Let's express that in
> the number of flip-flops or registers:
>
> CPLDs are good for up to 200 flip-flops, they get disproportionally
> expensive for larger designs.
> Modern FPGAs start at 2,000 flip-flops, and go up to to 200,000
> flip-flops, plus many other circuits, like RAM, multipliers etc.
>
> CoolRunner CPLDs offer extremely low power consumption, and small
> physical size, and low cost for the smallest parts.
> FPGAs fit a much wider range of applications.
>
> The choice between the two technologies is usually quite clear-cut.
> Peter Alfke, Xilinx Applications
> =====================================
> Matt Clement wrote:
> > Hey guys/gals
> >
> > What are the advantages and disadvantages of using a CPLD instead of
using
> > an FPGA for a design?
> >
> > Thanks
>

Austin Lesea wrote:
> Matt,
>
> If you use a a cpld, you need to post in comp.arch.cpld
> 
> Austin

There is no comp.arch.cpld

Hendra

Hendra wrote:
> Austin Lesea wrote:
>> Matt,
>>
>> If you use a a cpld, you need to post in comp.arch.cpld
>>
>> Austin
> 
> There is no comp.arch.cpld
> 

I suspect he was being facetious, and just forgot the smiley ;)

Duane,

Yes, I apologize for my sarcasm.

I had just read the posting concerning newsgroups, and how to get the 
best answers from them.  This post was a classic example of someone who 
had not even had the foresight to do any research on their own.

Given that everyone who posts here has access to google (or any other 
search engine), it is generally annoying to see questions that could be 
answered by three minutes of browsing and reading.

Sarcasm is the weapon of the weak, and I should have been more civil,

Austin

Duane Clark wrote:

> Hendra wrote:
> 
>> Austin Lesea wrote:
>>
>>> Matt,
>>>
>>> If you use a a cpld, you need to post in comp.arch.cpld
>>>
>>> Austin
>>
>>
>> There is no comp.arch.cpld
>>
> 
> I suspect he was being facetious, and just forgot the smiley ;)
> 

but sarcasm is so much better than a pointy stick.

Simon

"austin" <austin@xilinx.com> wrote in message
news:dude5h$ar25@xco-news.xilinx.com...
> Duane,
>
> Yes, I apologize for my sarcasm.
>
> I had just read the posting concerning newsgroups, and how to get the
> best answers from them.  This post was a classic example of someone who
> had not even had the foresight to do any research on their own.
>
> Given that everyone who posts here has access to google (or any other
> search engine), it is generally annoying to see questions that could be
> answered by three minutes of browsing and reading.
>
> Sarcasm is the weapon of the weak, and I should have been more civil,
>
> Austin
>
> Duane Clark wrote:
>
> > Hendra wrote:
> >
> >> Austin Lesea wrote:
> >>
> >>> Matt,
> >>>
> >>> If you use a a cpld, you need to post in comp.arch.cpld
> >>>
> >>> Austin
> >>
> >>
> >> There is no comp.arch.cpld
> >>
> >
> > I suspect he was being facetious, and just forgot the smiley ;)
> >

Matt Clement wrote:
> Hey guys/gals
> 
> What are the advantages and disadvantages of using a CPLD instead of using 
> an FPGA for a design?

  The answer to the heading is "You wouldn't" - if 'a CPLD will do',
in engineering terms means meet/exceed the price performance levels of a 
FPGA.

  The more general answer, of when to choose FPGA or CPLD, changes over 
time.
  10 years ago, CPLDs were cheap, non volatile logic, but most had High 
Iccs. FPGAs were all SRAM based, and had low Static Iccs.

  Now, the distinction is much more blurred :
# There are FPGAs with on Chip FLASH, [Lattice, Actel]
# FPGA static Icc is no longer low, but can hit hundreds of mA (!)
#  Newest CPLDs from Altera, Lattice have FPGA fabric, but CPLD-like 
FLASH - but at the same time, they have moved up the 'smallest device' 
point, so there are no real low cost members in this family.
# Lowest power devices are now the CMOS structure ones from Xilinx,
   Lattice, Atmel.
# Above a certain Logic size, FPGAs tend to self-select over the
  thinning ranks of large CPLDs

  In many cases, designs have BOTH CPLD and FPGA, and the CPLD can
be used to Boot the FPGA, via cheaper memory, and/or to control
power off, to have deeper sleep modes.

-jg