On Saturday, September 28, 2019 at 9:29:54 AM UTC-7, HT-Lab wrote:> On 28/09/2019 15:02, Weng Tianxiang wrote: > > On Saturday, September 28, 2019 at 1:24:26 AM UTC-7, HT-Lab wrote: > >> On 28/09/2019 00:25, Weng Tianxiang wrote: > .. > >>> > > > > Hi Hans, > > > > I remember that you mentioned that you implemented a 8*8 port memory module using technique based on paper "Efficient Multi-Ported Memories for FPGAs". > > Hi Weng, > > I actually used the XOR variant (not multipumped) to implement a 4W8R > port. You can find the paper here: > > http://fpgacpu.ca/multiport/FPGA2012-LaForest-XOR-Paper.pdf > > and more papers on the main page: > > http://fpgacpu.ca/multiport/ > > > > > Can you disclose more details and your experiences about your implementation? And what is the best technique to design a CPU register file in your opinion? > > That all depends on your design. In my case I could use the XOR variant > as I have a pipelined design were I could latch the register file's read > request early on in the pipeline and then in a later stage XOR with the > new results for the write request. The XOR is the most area efficient > but was the most complicated to add to my design (due to data hazards > and the fact that each write request also needs a read request). > > > > > In my project, I need multiple 2-write and 2 read port memory, true dual port memory does not meet my requirement. I estimate that I need 4 RAM with each having 1-write and 1-read port. > > In that case forget about LaForest Et.al paper and simple use one of the > core wizards like Intel's MegaWizard, Xilinx's Coregen etc. You get 2W2R > area/speed optimised design with lots of configurable options. > > > > > Even though my project is still in logic design stage and there is no problem for me to simulate the logic, based on current logic design: an array can be read n times and written m times: when multiple writing to an array in a process I guess a simulator would only write any data at the written address once it meets an assignment statement that would guarantee the last write is valid if their writing addresses are same. > > The core wizards gives you the option what should happen if you > read/write to the same address. > > > > > The technique based on the paper needs n*m RAM blocks if each RAM block has one write and one read port. What role may a dual port memory block play? > > Not sure what you are asking, you need DPRAM's as the basic building > block for a a multi-port design. If you have the time I would suggest to > implement the various versions and see how they behave, I learned a lot > from it. > > Good luck, > Hans > www.ht-lab.com > > > > > > Thank you. > > > > Weng > >Hans, Thank you very much for your help and sharing your experience with me, and 2 links are valuable. I will spend time reading those specifications and papers carefully. Because VHDL has means to generate a n*m port code, so my if_2 idea is meaningless and dead. I am sorry for your times spent on those related posts.Of cause I learned a lot. Also thank Rick and JK for your time. Weng
Here is new definition for keyword "if_2", version 2.
Started by ●September 27, 2019
Reply by ●September 28, 20192019-09-28
Reply by ●September 29, 20192019-09-29
On 28/09/2019 21:27, Weng Tianxiang wrote:> On Saturday, September 28, 2019 at 9:29:54 AM UTC-7, HT-Lab wrote: >> On 28/09/2019 15:02, Weng Tianxiang wrote: >>> On Saturday, September 28, 2019 at 1:24:26 AM UTC-7, HT-Lab wrote: >>>> On 28/09/2019 00:25, Weng Tianxiang wrote: >> .. >>>>> >>> >>> Hi Hans, >>> >>> I remember that you mentioned that you implemented a 8*8 port memory module using technique based on paper "Efficient Multi-Ported Memories for FPGAs". >> >> Hi Weng, >> >> I actually used the XOR variant (not multipumped) to implement a 4W8R >> port. You can find the paper here: >> >> http://fpgacpu.ca/multiport/FPGA2012-LaForest-XOR-Paper.pdf >> >> and more papers on the main page: >> >> http://fpgacpu.ca/multiport/ >> >>> >>> Can you disclose more details and your experiences about your implementation? And what is the best technique to design a CPU register file in your opinion? >> >> That all depends on your design. In my case I could use the XOR variant >> as I have a pipelined design were I could latch the register file's read >> request early on in the pipeline and then in a later stage XOR with the >> new results for the write request. The XOR is the most area efficient >> but was the most complicated to add to my design (due to data hazards >> and the fact that each write request also needs a read request). >> >>> >>> In my project, I need multiple 2-write and 2 read port memory, true dual port memory does not meet my requirement. I estimate that I need 4 RAM with each having 1-write and 1-read port. >> >> In that case forget about LaForest Et.al paper and simple use one of the >> core wizards like Intel's MegaWizard, Xilinx's Coregen etc. You get 2W2R >> area/speed optimised design with lots of configurable options. >> >>> >>> Even though my project is still in logic design stage and there is no problem for me to simulate the logic, based on current logic design: an array can be read n times and written m times: when multiple writing to an array in a process I guess a simulator would only write any data at the written address once it meets an assignment statement that would guarantee the last write is valid if their writing addresses are same. >> >> The core wizards gives you the option what should happen if you >> read/write to the same address. >> >>> >>> The technique based on the paper needs n*m RAM blocks if each RAM block has one write and one read port. What role may a dual port memory block play? >> >> Not sure what you are asking, you need DPRAM's as the basic building >> block for a a multi-port design. If you have the time I would suggest to >> implement the various versions and see how they behave, I learned a lot >> from it. >> >> Good luck, >> Hans >> www.ht-lab.com >> >> >>> >>> Thank you. >>> >>> Weng >>> > > Hans, > Thank you very much for your help and sharing your experience with me, and 2 links are valuable. I will spend time reading those specifications and papers carefully. > > Because VHDL has means to generate a n*m port code, so my if_2 idea is meaningless and dead. I am sorry for your times spent on those related posts.Of cause I learned a lot.No need to apologise, how many of us can say we have 4(?) granted US patents. Please continue to share your ideas and questions. Regards, Hans. www.ht-lab.com
Reply by ●September 29, 20192019-09-29
On Sunday, September 29,> No need to apologise, how many of us can say we have 4(?) granted US > patents. Please continue to share your ideas and questions. > > Regards, > Hans. > www.ht-lab.comHans, Thank you for your experience, help and encouragement. Your 4*8 memory module and a 4 computer system are a great achievement!!! Weng
