Hi all, I am a Verilog user. I want to use assertion based verification in my project. And I found OVL(Open Verification library). Do you think which one of the OVL is better? Verilog, PSL or SystemVerilog? And I heard SystemVerilog have the ABV feature? Why OVL supply ABV in SystemVerilog again? Best regards, Davy
Verilog, PSL or SystemVerilog of OVL?
Started by ●March 27, 2006
Reply by ●March 28, 20062006-03-28
I'd recommend you to go for SystemVerilog, as it's the hardware language of the future. Joe, LogicSim - Your Personal Verilog Simulator http://www.logicsim.com Davy wrote:> Hi all, > > I am a Verilog user. > I want to use assertion based verification in my project. And I found > OVL(Open Verification library). > > Do you think which one of the OVL is better? Verilog, PSL or > SystemVerilog? > > And I heard SystemVerilog have the ABV feature? Why OVL supply ABV in > SystemVerilog again? > > Best regards, > Davy
Reply by ●March 28, 20062006-03-28