Altera Stratix II GX LVDS max speed

I had spoke with Charley Pryor at Altera a few months back and had
asked about running a 16-bit data bus into a Stratix II and what sort
of speeds we could expext to run it at.  He had made the statement that
they had designs running in the 1GHz range and that they had some
in-house designs running at 2GHz.  Looking at the data sheets from Jan.
05. they show the LVDS only being rated to 840 Mbps.   Interesting
enough I am having a hard time finding any designs where people have
used the Altera parts at these speeds.

I am curious if any of you have run any wide busses into a Stratix II
near the rated speed and what results you had.  Did you use the Altera
synthisis tool?  Was there any hidden problems to get the design to
work?   Any information would be helpful.  Thanks

> I am curious if any of you have run any wide busses into a Stratix II
> near the rated speed and what results you had.  Did you use the Altera
> synthisis tool?  Was there any hidden problems to get the design to
> work?   Any information would be helpful.  Thanks
>
My design  has two FPGAs each with 10 input and 10 output SERDES channels 
running 8:1 @ 100 MHz for 800 Mbps per channel.  The two FPGAs are both 
Stratix II devices (2S30 and 2S60) on the same circuit board ~1 inch apart. 
So adding it all up I guess that would be 16 Gbps going back and forth. 
Since the connection was physically so short and on the same circuit board 
it was darn near the ideal setting for running high speed signals.

For the most part everything worked just fine, my only gotcha was that the 
relationship between when a particular bit comes out and the clock is not 
defined on the receiver side (although to me looking at the spec it 
certainly seemed to be to be).  This required adding in some code to get the 
receivers 'bit aligned' properly.  The good thing was that I was able to 
find this really early on in simulation long before I had a board.  See the 
'Doubt about SERDES' thread from 3/31 for more on that.  Other than that it 
all seems to be working.

I used Quartus 4.x and 5.x with no problems related to SERDES.

KJ 

Hi,

According to the link (1) below, Stratix II LVDS I/Os are rated at 1.04
Gbps.  If you look at link (2) below, we show some nice eye diagrams at
1.0 Gbps.  And that's not Stratix II GX.

Stratix II GX is shipping now, and its clock-data recovery (CDR) I/Os
are operating beautifully at 6.375 Gbps and 3.125 Gbps.  See link (3)
for some characterization results.  In addition, SII GX will operate at
1 Gbps just like Stratix II (4).

Referenced links:
(1)
http://www.altera.com/products/devices/stratix2/features/io/st2-source_synch.htm
(2)
http://www.altera.com/technology/signal/devices/stratix2/st2-signal-performance.html
(3)
http://www.altera.com/technology/signal/devices/stratix2gx/character/sgl-s2gx-character.html
(4)
http://www.altera.com/products/devices/stratix2gx/features/io/s2gx-source_synch.html

Regards,

Paul Leventis
Altera Corp.

If I wanted to just run a single clock and 16 synchronous data lines
into a Stratix device is there no way to make this work?  All the
information I am finding uses the SERDES.   I am interested in seeing
something more like Xilinx and National were demonstrating last month
with the Virtex but with a Stratix device.

Paul Leventis wrote:

> Referenced links:
> (1)
> http://www.altera.com/products/devices/stratix2/features/io/st2-source_synch.htm
that's missing the trailing 'L':
 
 
http://www.altera.com/products/devices/stratix2/features/io/st2-source_synch.html

Hi,

You'll need to deserialize (via a SERDES) since you can't operate the
FPGA core at 1 Ghz.  You still need only provide the device your 1
clock and 16 data lines, and the SERDES does the rest.  You can also
use dynamic phase alignmnet circuitry (DPA) if you want, but you don't
have to.  In its simplest form, all the SERDES block does in this case
is deserialize the data stream by between a factor of 2 and 10 to slow
it down to a rate you can handle in the core.

Regards,

Paul

Talking with the local apps. eng. it sounds like the speeds may be more
in the 2-300MHz range.  Time to do some reading....

It appears that the Stratix II is not going to be fast enough for the
first stage.  The primary problem is the lack of being able to support
a synchronous parallel bus.  Looking in the October 2005 Stratix II GX
handbook, the fastest reference clock appears to be 622MHz, far below
where I want to run at.  I could run a slower clock, use the SERDES to
multiply it up and resync the data and expand it out as you suggest,
but this really does not make a lot of sense.  The clock already has
phase noise under 5pS rms (from testing) and the data would be matched
going to the device.   I tried the SERDES approach you mentioned with
the Quartus tools using the Stratix II as a target device (even though
we have a full license for Quartus the tool requires TalkBack spyware
when targeting a GX device) and it seems to work.  I tried to set the
clock to the frequency I am interested in and the tool barks back with
an error.   I then tried a very simple approach of just using clocked
register but no luck.

I have seen a few Virtex 4 designs now that directly run a parallel bus
at the speeds I am interested in.  I am a bit gun shy after all the
problems we have seen with Xilinx over the years, but they seem to be a
better fit for this application.

If you have any other ideas, I would be interested in hearing them.

lecroy7200@chek.com wrote:
> It appears that the Stratix II is not going to be fast enough for the
> first stage.  The primary problem is the lack of being able to support
> a synchronous parallel bus.  Looking in the October 2005 Stratix II GX
> handbook, the fastest reference clock appears to be 622MHz, far below
> where I want to run at.  I could run a slower clock, use the SERDES to
> multiply it up and resync the data and expand it out as you suggest,
> but this really does not make a lot of sense.  The clock already has
> phase noise under 5pS rms (from testing) and the data would be matched
> going to the device.   I tried the SERDES approach you mentioned with
> the Quartus tools using the Stratix II as a target device (even though
> we have a full license for Quartus the tool requires TalkBack spyware
> when targeting a GX device) and it seems to work.  I tried to set the
> clock to the frequency I am interested in and the tool barks back with
> an error.   I then tried a very simple approach of just using clocked
> register but no luck.
>
> I have seen a few Virtex 4 designs now that directly run a parallel bus
> at the speeds I am interested in.  I am a bit gun shy after all the
> problems we have seen with Xilinx over the years, but they seem to be a
> better fit for this application.
>
> If you have any other ideas, I would be interested in hearing them.


You might want to take a look at the Lattice SC device its PURESPEED IO
has 2 Gbps throughput per differential I/O pair.
http://www.latticesemi.com/products/fpga/sc/index.cfm