Data Validity and Freshness

Hi all,

I am trying to interface a ADC with FPGA through SPI interface. FPGA
will have SPI slave implemmented. Once i receive the data from ADC i am
required to have some kind of data validity and freshness check. One
way to check validity is to have data parity embedded with data but ARE
THERE ANY OTHER OPTIONS because parity is prone to bit(s) error. Also i
am required to have some logic for freshness. Please any suggestions or
directions will be apperitiated.

Thanks.

I read a little bit on this topic and found points which are as follow:

1. Sender should be repsonsible to have a validity bit set with each
frame to show the frame has valid data.
2. Sender should compute an incremented CRC for each data frame and
attach it with sending data for freshness.
3. Receiver should extract the CRC and see if the CRC has incremented
than data is fresh otherwise data is not freshed.
4. Receiver should discard any incomming data if the validity criteria
sent by the sender fails to satisfies.

Now any more suggestions for checking data validity and freshness