LVDS in Cyclone-II

Started by John_H April 5, 2006
Hello folks,

I may be starting my first Altera design in a few years but I was 
disappointed to find that the Cyclone-II LVDS drivers aren't true 
differential drives: an external resistor network is needed to produce 
proper LVDS levels like in the "old days."

Does anyone here have experience with the LVDS drivers?  I imagine I'll end 
up with 0603 resistors rather than a Bourns network, for instance.  What 
have others used?  Was there any problem driving these 2.5V pins at LVDS 
rates in power supply noise or EMI?

I don't have a huge count of output signals so it's reasonable from a space 
standpoint.  The data sheet declares 640 Mbps LVDS transmit rates.

Also for receive... my glances through the Cyclone-II data sheet seem to 
indicate off-chip receive terminations are needed but I saw a post from 
Antti that said there were on-chip terminations.  Did I miss something?  Are 
on-chip terminations available for the Cyclone-II LVDS inputs?

The Spartan3E I/O solution is quite possibly better but pricing might push 
me back to brand A for this next design.

Any thoughts?

Thanks,
John Handwork 


The Spartan-3E I/O do not require external resistors for LVDS or RSDS
outputs, which simplifies board routing, number of vias, reliability,
etc.

For Spartan-3E LVDS or RSDS inputs, you can either use a 100-ohm
external termination resistor or the internal DIFF_TERM resistor built
into each pair, which is nominally 120 ohms.

Just FYI, we just recently released the following application note and
reference design on Spartan-3E for LVDS display applications.  It is
even simpler on 4:1, 8:1, etc. designs.

XAPP485:  1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to 666
Mbps
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=-1209837&show=xapp485

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation:  The World's Lowest-Cost FPGAs.

The Spartan3E LVDS approach is what I've grown to "expect:" a fully 
integrated solution.  The Spartan3E should give great results for those 
signals in spite of the capacitance issues that nag at other engineers.

So now I wonder about the competitor's suboptimal solution.


"Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com> 
wrote in message 
news:1144260012.858146.36290@g10g2000cwb.googlegroups.com...
> The Spartan-3E I/O do not require external resistors for LVDS or RSDS > outputs, which simplifies board routing, number of vias, reliability, > etc. > > For Spartan-3E LVDS or RSDS inputs, you can either use a 100-ohm > external termination resistor or the internal DIFF_TERM resistor built > into each pair, which is nominally 120 ohms. > > Just FYI, we just recently released the following application note and > reference design on Spartan-3E for LVDS display applications. It is > even simpler on 4:1, 8:1, etc. designs. > > XAPP485: 1:7 Deserialization in Spartan-3E FPGAs at Speeds Up to 666 > Mbps >
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=-1209837&show=xapp485
> > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/-3E FPGAs > http://www.xilinx.com/spartan3e > --------------------------------- > The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs. >
John_H wrote:
> > The Spartan3E should give great results for those signals in spite of the > capacitance issues that nag at other engineers. >
Well, outputs don't have as much of a problem with Cpin as have inputs driven from a fast logic family; but you already know that :) IIRC, the Lattice ECP2 have current mode LVDS drivers and ~8pF Cin. I've been hoping that the removal of DCI from S3E has improved Cin; when Xilinx releases the S3E IBIS models, we can get a better idea. It's interesting to contrast the datasheet C values for the two families: Cyclone-II Cio 6 pF (typ) user I/O Clvds 6 pF (typ) user I/O with LVDS Cvref 21 pF (typ) user I/O with Vref function Cclk 5 pF (typ) global clock input Spartan-3E Cin 3 pF (min) 10 pF (max) Which makes no distinction between input only pins, I/O pins, global clock input pins, left/right side clock pins, dual mode config pins, Vref pins, dedicated config pins, etc. Other S3E notes: - the strangely low SSO limit (4) for the current mode drivers has reappeared for some of the S3E family, after improving in the latest S3 family SSO tables - no IBIS models !! - I haven't spotted any characterization data for the DT terminator accuracy; just the ~120 ohm number with no min or max limits Brian
John_H wrote:
> Hello folks, > > I may be starting my first Altera design in a few years but I was > disappointed to find that the Cyclone-II LVDS drivers aren't true > differential drives: an external resistor network is needed to produce > proper LVDS levels like in the "old days." > > Does anyone here have experience with the LVDS drivers? I imagine I'll end > up with 0603 resistors rather than a Bourns network, for instance. What > have others used?
You could use the quad-smd's = 4 resistors in 1206 or 0805 ? -jg
Jim Granville wrote:
> John_H wrote: > >> Hello folks, >> >> I may be starting my first Altera design in a few years but I was >> disappointed to find that the Cyclone-II LVDS drivers aren't true >> differential drives: an external resistor network is needed to produce >> proper LVDS levels like in the "old days." >> >> Does anyone here have experience with the LVDS drivers? I imagine >> I'll end up with 0603 resistors rather than a Bourns network, for >> instance. What have others used? > > > You could use the quad-smd's = 4 resistors in 1206 or 0805 ? > > -jg
I could use "a Bourns network" or the like. I anticipate using 0603s because they're small, available, routable. Unless there's experience that says these tiny discretes should, indeed, be a resistor network instead. I could use the quad-smd's. Is there a reason I should? Shouldn't? I'm hoping more for tidbits of experience rather than good ideas. Thanks for the thoughts.
Brian Davis wrote:
> - the strangely low SSO limit (4) for the current mode drivers has > reappeared for some of the S3E family, after improving in the > latest S3 family SSO tables
I noticed the SSO numbers but they don't affect me this round. The specs are "per power/ground pair" which is ample on the BGA packages (7 effective pairs per bank?) but still allows 8 SSOs on the wireframe parts (2 pairs ber bank). I interpreted that as LVDS pairs, so 16 signal lines per bank. Oops. I just remembered - there are only 4 banks on the Spartan3E. Yikes! The pairs per bank are 1.4x-2x the Spartan3 values so it looks like they may be legit. I sure hope those SSOs get changed!!! ____ Larger Cyclone-IIs have 8 banks but they also have some strange single-ended / differential restrictions within a bank. Odd stuff. Maybe not a problem, but odd. The Lattice parts are looking *nice* but are a bit low on memory for what I want to prototype. I was looking seriously at the new devices until I realized the breadth of the memory disparity. I could use a larger part with more memory but then the costs go up.
John_H wrote:
> Jim Granville wrote: > >> John_H wrote: >> >>> Hello folks, >>> >>> I may be starting my first Altera design in a few years but I was >>> disappointed to find that the Cyclone-II LVDS drivers aren't true >>> differential drives: an external resistor network is needed to >>> produce proper LVDS levels like in the "old days." >>> >>> Does anyone here have experience with the LVDS drivers? I imagine >>> I'll end up with 0603 resistors rather than a Bourns network, for >>> instance. What have others used? >> >> >> >> You could use the quad-smd's = 4 resistors in 1206 or 0805 ? >> >> -jg > > > I could use "a Bourns network" or the like. I anticipate using 0603s > because they're small, available, routable. Unless there's experience > that says these tiny discretes should, indeed, be a resistor network > instead. > > I could use the quad-smd's. Is there a reason I should? Shouldn't? > > I'm hoping more for tidbits of experience rather than good ideas.
Mainly it's a packing density issue. IIRC the pitch on the Quads, matches that of common TQFP packages. They are also on the right part of the price curve, and slash the resistor placement bill by 3/4. -jg
Jim Granville wrote:
> John_H wrote: >> > I could use "a Bourns network" or the like. I anticipate using 0603s > > because they're small, available, routable. Unless there's experience > > that says these tiny discretes should, indeed, be a resistor network > > instead. > > > > I could use the quad-smd's. Is there a reason I should? Shouldn't? > > > > I'm hoping more for tidbits of experience rather than good ideas. > > Mainly it's a packing density issue. IIRC the pitch on the > Quads, matches that of common TQFP packages. > They are also on the right part of the price curve, and > slash the resistor placement bill by 3/4.
When I'm doing a very dense board design, I typically use 0402 resistors because they can be tucked almost anywhere at will. IE, you aren't contrained to finding place(s) to set down one or more quad packs. Said another way, on average, I think I get better placement on densely routed boards using single 0402's. If you lower the density though, it probably makes sense to go to packs assuming your manufacturing house can make the boards without solder shorts on the packs. Have fun, Marc
John_H wrote:
> Brian Davis wrote: > > - the strangely low SSO limit (4) for the current mode drivers has > > reappeared for some of the S3E family, after improving in the > > latest S3 family SSO tables > > I noticed the SSO numbers but they don't affect me this round. The > specs are "per power/ground pair" which is ample on the BGA packages (7 > effective pairs per bank?) but still allows 8 SSOs on the wireframe > parts (2 pairs ber bank). I interpreted that as LVDS pairs, so 16 > signal lines per bank. > > Oops. > > I just remembered - there are only 4 banks on the Spartan3E. Yikes! > The pairs per bank are 1.4x-2x the Spartan3 values so it looks like they > may be legit. > > I sure hope those SSOs get changed!!!
Which package did you plan to use and how many LVDS output pairs are required? The different SSO numbers on the quad-flat packages are purposely lower due to their merely average signal integrity. The BGA packages have superior signal integrity. Here's how you would calculate the recommended limit using the data sheet values. http://www.xilinx.com/bvdocs/publications/ds312.pdf Let's assume that you're using the TQ144 package, which has the equivalent of 2 VCC/GND pairs per bank (Table 92, page 133). Then, go to the LVDS_25 section in Table 93 (on page 134), indicating that you can have 4 LVDS _output pairs_ (emphasis included) per power ground pair. Multiply the values together to arrive at 8 LVDS _output pairs_ on a bank in the TQ144 package. Again, the SSOs are a recommendation, but let's keep it to 8 pairs, which equations to 16 I/O pins. There are only ~23 I/O on a package edge in the TQ144. The Input-only pins are not available as outputs. Also, SSOs are only for outputs. You can have as many LVDS inputs that will fit in an I/O bank. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs http://www.xilinx.com/spartan3e --------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.