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Vending Machine

Started by Esma ●June 15, 2023
my project designing a vending machine that sells a candy for 40 cent. it accept olny 5 cent(N) and 10 cent (D). and the candy  i wrote this code for this but i couldn't write a testbench to see waveform Can you help me please 
library ieee;
use ieee.std_logic_1164.all;

entity vending_machine is
  port (
    CLK, RESET: in std_logic;
    N, D: in std_logic;
    output: out std_logic;
    change: out std_logic_vector(5 downto 0)
  );
end vending_machine;

architecture process_3 of vending_machine is
  type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9);
  signal state, next_state: state_type;

begin
  process (CLK, RESET)
  begin
    if (RESET = '1') then
      state <= s0;
    elsif (rising_edge(CLK)) then
      state <= next_state;
    end if;
  end process;

  process (state, N, D)
  begin
    case state is
      when s0 =>
        if N = '0' and D = '0' then
          next_state <= s0;
          output <= '0';
          change <= "000000";
        elsif N = '0' and D = '1' then
          next_state <= s1;
          output <= '0';
          change <= "000000";
        elsif N = '1' and D = '0' then
          next_state <= s2;
          output <= '0';
          change <= "000000";
        end if;
        
      when s1 =>
        if N = '0' and D = '0' then
          next_state <= s0;
          output <= '0';
          change <= "000101";
        elsif N = '0' and D = '1' then
          next_state <= s2;
          output <= '0';
          change <= "000000";
        elsif N = '1' and D = '0' then
          next_state <= s3;
          output <= '0';
          change <= "000000";
        end if;
        
      when s2 =>
        if N = '0' and D = '0' then
          next_state <= s0;
          output <= '0';
          change <= "001010";
        elsif N = '0' and D = '1' then
          next_state <= s3;
          output <= '0';
          change <= "000000";
        elsif N = '1' and D = '0' then
          next_state <= s4;
          output <= '0';
          change <= "000000";
        end if;
        
      when s3 =>
        if N = '0' and D = '0' then
          next_state <= s0;
          output <= '0';
          change <= "001111";
        elsif N = '0' and D = '1' then
          next_state <= s4;
          output <= '0';
          change <= "000000";
        elsif N = '1' and D = '0' then
          next_state <= s5;
          output <= '0';
          change <= "000000";
        end if;
        
      when s4 =>
        if N = '0' and D = '0' then
          next_state <= s0;
          output <= '0';
          change <= "010100";
        elsif N = '0' and D = '1' then
          next_state <= s5;
          output <= '0';
          change <= "000000";
        elsif N = '1' and D = '0' then
          next_state <= s6;
          output <= '0';
          change <= "000000";
        end if;
        
      when s5 =>
        if N = '0' and D = '0' then
          next_state <= s0;
          output <= '0';
          change <= "011001";
        elsif N = '0' and D = '1' then
          next_state <= s6;
          output <= '0';
          change <= "000000";
        elsif N = '1' and D = '0' then
          next_state <= s7;
          output <= '0';
          change <= "000000";
        end if;
        
      when s6 =>
        if N = '0' and D = '0' then
          next_state <= s0;
          output <= '0';
          change <= "011110";
        elsif N = '0' and D = '1' then
          next_state <= s7;
          output <= '0';
          change <= "000000";
        elsif N = '1' and D = '0' then
          if RESET = '1' then
            next_state <= s0;
            output <= '1';
            change <= "000000";
          else
            next_state <= s8;
            output <= '1';
            change <= "000000";
          end if;
        end if;
        
      when s7 =>
if N = '0' and D = '0' then
          next_state <= s0;
          output <= '0';
          change <= "100011";
elsif N = '0' and D = '1' then
         if RESET = '1' then
            next_state <= s0;
            output <= '1';
            change <= "000101";
          else
            next_state <= s9;
            output <= '1';
            change <= "000101";
           end if; 
elsif N = '1' and D = '0' then
           if RESET = '1' then
            next_state <= s0;
            output <= '1';
            change <= "000000";
          else
            next_state <= s9;
            output <= '1';
            change <= "000000";
         end if; 
end if;     
      when s8 =>
        if N = '0' and D = '0' then
          if RESET = '1' then
            next_state <= s0;
            output <= '1';
            change <= "000000";
          else
            next_state <= s8;
            output <= '1';
            change <= "000000";
          end if;
        end if;
        
      when s9 =>
        if RESET = '1' then
          next_state <= s0;
          output <= '1';
          change <= "000101";
        else
          next_state <= s9;
          output <= '0';
          change <= "000000";
        end if;
        
      when others =>
        next_state <= s0;
        output <= '0';
        change <= "000000";
    end case;
  end process;

end architecture process_3;
Reply by gnua...@gmail.com ●June 16, 20232023-06-16
On Thursday, June 15, 2023 at 2:15:19&#8239;PM UTC-4, Esma wrote:

> my project designing a vending machine that sells a candy for 40 cent. it accept olny 5 cent(N) and 10 cent (D). and the candy i wrote this code for this but i couldn't write a testbench to see waveform Can you help me please 
> library ieee; 
> use ieee.std_logic_1164.all; 
> 
> entity vending_machine is 
> port ( 
> CLK, RESET: in std_logic; 
> N, D: in std_logic; 
> output: out std_logic; 
> change: out std_logic_vector(5 downto 0) 
> ); 
> end vending_machine; 
> 
> architecture process_3 of vending_machine is 
> type state_type is (s0, s1, s2, s3, s4, s5, s6, s7, s8, s9); 
> signal state, next_state: state_type; 
> 
> begin 
> process (CLK, RESET) 
> begin 
> if (RESET = '1') then 
> state <= s0; 
> elsif (rising_edge(CLK)) then 
> state <= next_state; 
> end if; 
> end process; 
> 
> process (state, N, D) 
> begin 
> case state is 
> when s0 => 
> if N = '0' and D = '0' then 
> next_state <= s0; 
> output <= '0'; 
> change <= "000000"; 
> elsif N = '0' and D = '1' then 
> next_state <= s1; 
> output <= '0'; 
> change <= "000000"; 
> elsif N = '1' and D = '0' then 
> next_state <= s2; 
> output <= '0'; 
> change <= "000000"; 
> end if; 
> 
> when s1 => 
> if N = '0' and D = '0' then 
> next_state <= s0; 
> output <= '0'; 
> change <= "000101"; 
> elsif N = '0' and D = '1' then 
> next_state <= s2; 
> output <= '0'; 
> change <= "000000"; 
> elsif N = '1' and D = '0' then 
> next_state <= s3; 
> output <= '0'; 
> change <= "000000"; 
> end if; 
> 
> when s2 => 
> if N = '0' and D = '0' then 
> next_state <= s0; 
> output <= '0'; 
> change <= "001010"; 
> elsif N = '0' and D = '1' then 
> next_state <= s3; 
> output <= '0'; 
> change <= "000000"; 
> elsif N = '1' and D = '0' then 
> next_state <= s4; 
> output <= '0'; 
> change <= "000000"; 
> end if; 
> 
> when s3 => 
> if N = '0' and D = '0' then 
> next_state <= s0; 
> output <= '0'; 
> change <= "001111"; 
> elsif N = '0' and D = '1' then 
> next_state <= s4; 
> output <= '0'; 
> change <= "000000"; 
> elsif N = '1' and D = '0' then 
> next_state <= s5; 
> output <= '0'; 
> change <= "000000"; 
> end if; 
> 
> when s4 => 
> if N = '0' and D = '0' then 
> next_state <= s0; 
> output <= '0'; 
> change <= "010100"; 
> elsif N = '0' and D = '1' then 
> next_state <= s5; 
> output <= '0'; 
> change <= "000000"; 
> elsif N = '1' and D = '0' then 
> next_state <= s6; 
> output <= '0'; 
> change <= "000000"; 
> end if; 
> 
> when s5 => 
> if N = '0' and D = '0' then 
> next_state <= s0; 
> output <= '0'; 
> change <= "011001"; 
> elsif N = '0' and D = '1' then 
> next_state <= s6; 
> output <= '0'; 
> change <= "000000"; 
> elsif N = '1' and D = '0' then 
> next_state <= s7; 
> output <= '0'; 
> change <= "000000"; 
> end if; 
> 
> when s6 => 
> if N = '0' and D = '0' then 
> next_state <= s0; 
> output <= '0'; 
> change <= "011110"; 
> elsif N = '0' and D = '1' then 
> next_state <= s7; 
> output <= '0'; 
> change <= "000000"; 
> elsif N = '1' and D = '0' then 
> if RESET = '1' then 
> next_state <= s0; 
> output <= '1'; 
> change <= "000000"; 
> else 
> next_state <= s8; 
> output <= '1'; 
> change <= "000000"; 
> end if; 
> end if; 
> 
> when s7 => 
> if N = '0' and D = '0' then 
> next_state <= s0; 
> output <= '0'; 
> change <= "100011"; 
> elsif N = '0' and D = '1' then 
> if RESET = '1' then 
> next_state <= s0; 
> output <= '1'; 
> change <= "000101"; 
> else 
> next_state <= s9; 
> output <= '1'; 
> change <= "000101"; 
> end if; 
> elsif N = '1' and D = '0' then 
> if RESET = '1' then 
> next_state <= s0; 
> output <= '1'; 
> change <= "000000"; 
> else 
> next_state <= s9; 
> output <= '1'; 
> change <= "000000"; 
> end if; 
> end if; 
> when s8 => 
> if N = '0' and D = '0' then 
> if RESET = '1' then 
> next_state <= s0; 
> output <= '1'; 
> change <= "000000"; 
> else 
> next_state <= s8; 
> output <= '1'; 
> change <= "000000"; 
> end if; 
> end if; 
> 
> when s9 => 
> if RESET = '1' then 
> next_state <= s0; 
> output <= '1'; 
> change <= "000101"; 
> else 
> next_state <= s9; 
> output <= '0'; 
> change <= "000000"; 
> end if; 
> 
> when others => 
> next_state <= s0; 
> output <= '0'; 
> change <= "000000"; 
> end case; 
> end process; 
> 
> end architecture process_3;


The bit that is important in the test bench is this: 

entity vending_machine is
  port (
    CLK, RESET: in std_logic;
    N, D: in std_logic;
    output: out std_logic;
    change: out std_logic_vector(5 downto 0)
  );
end vending_machine;

You need to treat your design as a component in the test bench.  Write code to drive the clock, the N and the D inputs as you choose.  You can examine the outputs manually in the simulator, or, if you wish to analyze the design carefully, you can write code to verify the outputs automatically.  The statement to assist with this is: 

assert(exp); 

Where exp is an expression that should evaluate to TRUE.  If not, the assert statement will print to the simulation output.  You can combine assert with report to give a specific text output indicating exactly what is wrong, including the value of the thing being tested. 

-- 

  Rick C.

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