Can't get my Verilog Peripheral to import into XPS! Any tricks?

Hello -

I am trying to write a custom peripheral using Verilog and version 8.1
of the  Xilinx tool kits (ISE and XPS).  It is my understanding that
only the user_logic component of the peripheral can be developed in
Verilog, not sure if that is correct or not.  Anyway, I used the XPS
create custom peripheral tool to create the skeleton of the peripheral.
 I was careful to select the option to generate the user_logic stub in
Verilog rather than VHDL.  At which point I received a dialog box
warning that the Verilog stub will be limited capabilities, I went
ahead with the Verilog stub.  Then, using the ISE,  I added the
required ports etc to the top level VHDL code and added my Verilog code
to the user_logic component.

Once I confirmed all of the syntax was correct, I went back to XPS and
attempted to import the existing peripheral back into the project.  I
selected the standard options.  I also selectd the 'MIXED' option
for the question asking which HDL languages were used to implement the
peripheral.

I also realized that for some reason the create custom peripherial
wizard did not seem to include my user_logic module in the PAO file.
So I manually edited the file and added the following line:

lib opb_DVIReceiver_v1_00_a user_logic Verilog

I was a bit surprised that I had to do this, because in the past,
I've created customer peripherals in VHDL and found that the
user_logic entry was automatically placed into the PAO file.  Anyway, I
completed the import custom peripheral wizard and then added the IP to
my XPS project.  I specified the addresses, and tied in the required
ports etc.  All SEEMED well.  However when I tried to generate the
bitstream, I received the following error:

ERROR:NgdBuild:604 - logical block
   'opb_dvireceiver_0/opb_dvireceiver_0/USER_LOGIC_I' with type
'user_logic'
   could not be resolved. A pin name misspelling can cause this, a
missing edif
   or ngc file, or the misspelling of a type name. Symbol 'user_logic'
is not
   supported in target 'virtex2p'.

I have searched the net for information regarding this error message
and found several mentions of it, however none of which seemed to help.

There MUST be some information somewhere that explains how to import
custome peripherals that make use of a user_logic component written in
Verilog, but I have yet to be able to find anything.  I would GREATLY
appreciate it if someone out there could point me in the right
direction.  

Thanks in advance,

Jim

Jim,

Have you looked into the MPD file for your peripheral? I am guessing, but
the relevant options are probably as follows:

OPTION HDL = MIX
OPTION STYLE = HDL
OPTION RUN_NGCBUILD = TRUE

/Mikhail


<jhouse@btmd.com> wrote in message
news:1152719230.706099.6480@i42g2000cwa.googlegroups.com...
> Hello -
>
> I am trying to write a custom peripheral using Verilog and version 8.1
> of the  Xilinx tool kits (ISE and XPS).  It is my understanding that
> only the user_logic component of the peripheral can be developed in
> Verilog, not sure if that is correct or not.  Anyway, I used the XPS
> create custom peripheral tool to create the skeleton of the peripheral.
>  I was careful to select the option to generate the user_logic stub in
> Verilog rather than VHDL.  At which point I received a dialog box
> warning that the Verilog stub will be limited capabilities, I went
> ahead with the Verilog stub.  Then, using the ISE,  I added the
> required ports etc to the top level VHDL code and added my Verilog code
> to the user_logic component.
>
> Once I confirmed all of the syntax was correct, I went back to XPS and
> attempted to import the existing peripheral back into the project.  I
> selected the standard options.  I also selectd the 'MIXED' option
> for the question asking which HDL languages were used to implement the
> peripheral.
>
> I also realized that for some reason the create custom peripherial
> wizard did not seem to include my user_logic module in the PAO file.
> So I manually edited the file and added the following line:
>
> lib opb_DVIReceiver_v1_00_a user_logic Verilog
>
> I was a bit surprised that I had to do this, because in the past,
> I've created customer peripherals in VHDL and found that the
> user_logic entry was automatically placed into the PAO file.  Anyway, I
> completed the import custom peripheral wizard and then added the IP to
> my XPS project.  I specified the addresses, and tied in the required
> ports etc.  All SEEMED well.  However when I tried to generate the
> bitstream, I received the following error:
>
> ERROR:NgdBuild:604 - logical block
>    'opb_dvireceiver_0/opb_dvireceiver_0/USER_LOGIC_I' with type
> 'user_logic'
>    could not be resolved. A pin name misspelling can cause this, a
> missing edif
>    or ngc file, or the misspelling of a type name. Symbol 'user_logic'
> is not
>    supported in target 'virtex2p'.
>
> I have searched the net for information regarding this error message
> and found several mentions of it, however none of which seemed to help.
>
> There MUST be some information somewhere that explains how to import
> custome peripherals that make use of a user_logic component written in
> Verilog, but I have yet to be able to find anything.  I would GREATLY
> appreciate it if someone out there could point me in the right
> direction.
>
> Thanks in advance,
>
> Jim
>

Mikhail -

Thanks for the suggestions, they seem to have worked.  My question now
is how was I supposed to know to add these options to the MPD file?  I
created the shell of the peripheral using the EDK Create Peripheral
wizard, added a bit of Verilog code using the ISE and then re-imported
the modified peripheral using import peripheral EDK wizard.  All of
that resulted in the following options being placed in the MPD file:

###################################################################
##
## Name     : opb_DVIReceiver
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN opb_DVIReceiver

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER

Which resulted in the error mentioned in my original post.  Per your
suggestion, I manually edited the MPD file and added two of the options
you suggested (the option HDL MIXED was already there) resulting in the
following:

OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION STYLE = HDL
OPTION RUN_NGCBUILD = TRUE

Which, as I said, seems to be working.  I really feel that Xilinx needs
to document all of the little tricks that have to be done in order to
use a Verilog based custom peripheral.

Thanks for the help,

Jim

MM wrote:
> Jim,
>
> Have you looked into the MPD file for your peripheral? I am guessing, but
> the relevant options are probably as follows:
>
> OPTION HDL = MIX
> OPTION STYLE = HDL
> OPTION RUN_NGCBUILD = TRUE
>
> /Mikhail
>
>
> <jhouse@btmd.com> wrote in message
> news:1152719230.706099.6480@i42g2000cwa.googlegroups.com...
> > Hello -
> >
> > I am trying to write a custom peripheral using Verilog and version 8.1
> > of the  Xilinx tool kits (ISE and XPS).  It is my understanding that
> > only the user_logic component of the peripheral can be developed in
> > Verilog, not sure if that is correct or not.  Anyway, I used the XPS
> > create custom peripheral tool to create the skeleton of the peripheral.
> >  I was careful to select the option to generate the user_logic stub in
> > Verilog rather than VHDL.  At which point I received a dialog box
> > warning that the Verilog stub will be limited capabilities, I went
> > ahead with the Verilog stub.  Then, using the ISE,  I added the
> > required ports etc to the top level VHDL code and added my Verilog code
> > to the user_logic component.
> >
> > Once I confirmed all of the syntax was correct, I went back to XPS and
> > attempted to import the existing peripheral back into the project.  I
> > selected the standard options.  I also selectd the 'MIXED' option
> > for the question asking which HDL languages were used to implement the
> > peripheral.
> >
> > I also realized that for some reason the create custom peripherial
> > wizard did not seem to include my user_logic module in the PAO file.
> > So I manually edited the file and added the following line:
> >
> > lib opb_DVIReceiver_v1_00_a user_logic Verilog
> >
> > I was a bit surprised that I had to do this, because in the past,
> > I've created customer peripherals in VHDL and found that the
> > user_logic entry was automatically placed into the PAO file.  Anyway, I
> > completed the import custom peripheral wizard and then added the IP to
> > my XPS project.  I specified the addresses, and tied in the required
> > ports etc.  All SEEMED well.  However when I tried to generate the
> > bitstream, I received the following error:
> >
> > ERROR:NgdBuild:604 - logical block
> >    'opb_dvireceiver_0/opb_dvireceiver_0/USER_LOGIC_I' with type
> > 'user_logic'
> >    could not be resolved. A pin name misspelling can cause this, a
> > missing edif
> >    or ngc file, or the misspelling of a type name. Symbol 'user_logic'
> > is not
> >    supported in target 'virtex2p'.
> >
> > I have searched the net for information regarding this error message
> > and found several mentions of it, however none of which seemed to help.
> >
> > There MUST be some information somewhere that explains how to import
> > custome peripherals that make use of a user_logic component written in
> > Verilog, but I have yet to be able to find anything.  I would GREATLY
> > appreciate it if someone out there could point me in the right
> > direction.
> >
> > Thanks in advance,
> >
> > Jim
> >

jhouse@btmd.com wrote:
> Mikhail -
> 
> Thanks for the suggestions, they seem to have worked.  My question now
> is how was I supposed to know to add these options to the MPD file?  

I've made several peripherals with user_logic in Verilog. I've never had 
any problems with the tools as you describe. User_logic.v is always 
placed in the .pao for me, and I've never had to edit my .mpd file.


---
Joe Samson
Pixel Velocity

I just tried the proceedure once again, with version 8.1 of the tools,
and yes you are correct the user_logic.v was in the PAO, but again, the
two options:

OPTION STYLE = HDL
OPTION RUN_NGCBUILD = TRUE

We're not placed in the MPD file.  Are these options required?

jhouse@btmd.com wrote:
> Mikhail -
>
> Thanks for the suggestions, they seem to have worked.  My question now
> is how was I supposed to know to add these options to the MPD file?  I
> created the shell of the peripheral using the EDK Create Peripheral
> wizard, added a bit of Verilog code using the ISE and then re-imported
> the modified peripheral using import peripheral EDK wizard.  All of
> that resulted in the following options being placed in the MPD file:
>
> ###################################################################
> ##
> ## Name     : opb_DVIReceiver
> ## Desc     : Microprocessor Peripheral Description
> ##          : Automatically generated by PsfUtility
> ##
> ###################################################################
>
> BEGIN opb_DVIReceiver
>
> ## Peripheral Options
> OPTION IPTYPE = PERIPHERAL
> OPTION IMP_NETLIST = TRUE
> OPTION HDL = MIXED
> OPTION CORE_STATE = ACTIVE
> OPTION IP_GROUP = MICROBLAZE:PPC:USER
>
> Which resulted in the error mentioned in my original post.  Per your
> suggestion, I manually edited the MPD file and added two of the options
> you suggested (the option HDL MIXED was already there) resulting in the
> following:
>
> OPTION IPTYPE = PERIPHERAL
> OPTION IMP_NETLIST = TRUE
> OPTION HDL = MIXED
> OPTION CORE_STATE = ACTIVE
> OPTION IP_GROUP = MICROBLAZE:PPC:USER
> OPTION STYLE = HDL
> OPTION RUN_NGCBUILD = TRUE
>
> Which, as I said, seems to be working.  I really feel that Xilinx needs
> to document all of the little tricks that have to be done in order to
> use a Verilog based custom peripheral.
>
> Thanks for the help,
>
> Jim
>
> MM wrote:
> > Jim,
> >
> > Have you looked into the MPD file for your peripheral? I am guessing, but
> > the relevant options are probably as follows:
> >
> > OPTION HDL = MIX
> > OPTION STYLE = HDL
> > OPTION RUN_NGCBUILD = TRUE
> >
> > /Mikhail
> >
> >
> > <jhouse@btmd.com> wrote in message
> > news:1152719230.706099.6480@i42g2000cwa.googlegroups.com...
> > > Hello -
> > >
> > > I am trying to write a custom peripheral using Verilog and version 8.1
> > > of the  Xilinx tool kits (ISE and XPS).  It is my understanding that
> > > only the user_logic component of the peripheral can be developed in
> > > Verilog, not sure if that is correct or not.  Anyway, I used the XPS
> > > create custom peripheral tool to create the skeleton of the peripheral.
> > >  I was careful to select the option to generate the user_logic stub in
> > > Verilog rather than VHDL.  At which point I received a dialog box
> > > warning that the Verilog stub will be limited capabilities, I went
> > > ahead with the Verilog stub.  Then, using the ISE,  I added the
> > > required ports etc to the top level VHDL code and added my Verilog code
> > > to the user_logic component.
> > >
> > > Once I confirmed all of the syntax was correct, I went back to XPS and
> > > attempted to import the existing peripheral back into the project.  I
> > > selected the standard options.  I also selectd the 'MIXED' option
> > > for the question asking which HDL languages were used to implement the
> > > peripheral.
> > >
> > > I also realized that for some reason the create custom peripherial
> > > wizard did not seem to include my user_logic module in the PAO file.
> > > So I manually edited the file and added the following line:
> > >
> > > lib opb_DVIReceiver_v1_00_a user_logic Verilog
> > >
> > > I was a bit surprised that I had to do this, because in the past,
> > > I've created customer peripherals in VHDL and found that the
> > > user_logic entry was automatically placed into the PAO file.  Anyway, I
> > > completed the import custom peripheral wizard and then added the IP to
> > > my XPS project.  I specified the addresses, and tied in the required
> > > ports etc.  All SEEMED well.  However when I tried to generate the
> > > bitstream, I received the following error:
> > >
> > > ERROR:NgdBuild:604 - logical block
> > >    'opb_dvireceiver_0/opb_dvireceiver_0/USER_LOGIC_I' with type
> > > 'user_logic'
> > >    could not be resolved. A pin name misspelling can cause this, a
> > > missing edif
> > >    or ngc file, or the misspelling of a type name. Symbol 'user_logic'
> > > is not
> > >    supported in target 'virtex2p'.
> > >
> > > I have searched the net for information regarding this error message
> > > and found several mentions of it, however none of which seemed to help.
> > >
> > > There MUST be some information somewhere that explains how to import
> > > custome peripherals that make use of a user_logic component written in
> > > Verilog, but I have yet to be able to find anything.  I would GREATLY
> > > appreciate it if someone out there could point me in the right
> > > direction.
> > >
> > > Thanks in advance,
> > >
> > > Jim
> > >

jhouse@btmd.com wrote:
> I just tried the proceedure once again, with version 8.1 of the tools,
> and yes you are correct the user_logic.v was in the PAO, but again, the
> two options:
> 
> OPTION STYLE = HDL
> OPTION RUN_NGCBUILD = TRUE
> 
> We're not placed in the MPD file.  Are these options required?
They're not in any of my .MPD files.

---
Joe Samson
Pixel Velocity

jhouse@btmd.com wrote:
> Hello -
> 
> I am trying to write a custom peripheral using Verilog and version 8.1
> of the  Xilinx tool kits (ISE and XPS).  It is my understanding that
> only the user_logic component of the peripheral can be developed in
> Verilog, not sure if that is correct or not.  Anyway, I used the XPS
> create custom peripheral tool to create the skeleton of the peripheral.
>  I was careful to select the option to generate the user_logic stub in
> Verilog rather than VHDL.  At which point I received a dialog box
> warning that the Verilog stub will be limited capabilities, I went
> ahead with the Verilog stub.  Then, using the ISE,  I added the
> required ports etc to the top level VHDL code and added my Verilog code
> to the user_logic component.
> 
> Once I confirmed all of the syntax was correct, I went back to XPS and
> attempted to import the existing peripheral back into the project.  I
> selected the standard options.  I also selectd the 'MIXED' option
> for the question asking which HDL languages were used to implement the
> peripheral.
> 
> I also realized that for some reason the create custom peripherial
> wizard did not seem to include my user_logic module in the PAO file.
> So I manually edited the file and added the following line:
> 
> lib opb_DVIReceiver_v1_00_a user_logic Verilog
> 
> I was a bit surprised that I had to do this, because in the past,
> I've created customer peripherals in VHDL and found that the
> user_logic entry was automatically placed into the PAO file.  Anyway, I
> completed the import custom peripheral wizard and then added the IP to
> my XPS project.  I specified the addresses, and tied in the required
> ports etc.  All SEEMED well.  However when I tried to generate the
> bitstream, I received the following error:
> 
> ERROR:NgdBuild:604 - logical block
>    'opb_dvireceiver_0/opb_dvireceiver_0/USER_LOGIC_I' with type
> 'user_logic'
>    could not be resolved. A pin name misspelling can cause this, a
> missing edif
>    or ngc file, or the misspelling of a type name. Symbol 'user_logic'
> is not
>    supported in target 'virtex2p'.
> 
> I have searched the net for information regarding this error message
> and found several mentions of it, however none of which seemed to help.
> 
> There MUST be some information somewhere that explains how to import
> custome peripherals that make use of a user_logic component written in
> Verilog, but I have yet to be able to find anything.  I would GREATLY
> appreciate it if someone out there could point me in the right
> direction.  
> 
> Thanks in advance,
> 
> Jim
> 


Ha! I went through the same thing when I started with my own 
peripherals.  There is alot of practical stuff not documented.  Here is 
my general flow:

Use wizard to create templates

Write Verilog code, simulate, etc.

MANUALLY edit .mpd and .poa files to add any new verilog files for my source

run the import wizard, telling it to use the mpd or poa file that I edited.

import the peripheral.


I don't like the limited availability (and the big warning message 
abouyt to not use verilog) verilog examples.  It seems that they might 
dump verilog support....

-Eli

Eli Hughes wrote:
> 
> I don't like the limited availability (and the big warning message 
>  to not use verilog) of verilog examples.  It seems that they might 
> dump verilog support....
> 
> -Eli

They just added verilog support in 7.1i, so I doubt that the would drop 
it now. It would be nice to have verilog examples. I've generated VHDL 
versions just to see the example code.

---
Joe Samson