Driving a 30 bit wide LVTTL bus at 160MHz

Hello,

In my future design I could win a lot of pins if I could drive a bus at
160MHz. Because of bank restrictions and because this bus is connected
to a CPLD, I will have to use LVTTL.
Has anybody tried driving a bus in LVTTL at 160MHz?

I would prefer to use LVDS but the CPLD doesn't allow that. Lattice has
LVDS CPLDs but only the large CPLDs support LVDS inputs.

I am afraid that this bus will have a lot of EMI/EMC problems. What do
you think of it, should series termination be adequate to limit the
EMI/EMC problems?

best regards,
Dolphin

Simulate it. Hyperlynx is your friend!
HTH, Syms.
"Dolphin" <Karel.Deprez@gemidis.be> wrote in message 
news:1159368842.453549.244660@b28g2000cwb.googlegroups.com...
> Hello,
>
> In my future design I could win a lot of pins if I could drive a bus at
> 160MHz. Because of bank restrictions and because this bus is connected
> to a CPLD, I will have to use LVTTL.
> Has anybody tried driving a bus in LVTTL at 160MHz?
>
> I would prefer to use LVDS but the CPLD doesn't allow that. Lattice has
> LVDS CPLDs but only the large CPLDs support LVDS inputs.
>
> I am afraid that this bus will have a lot of EMI/EMC problems. What do
> you think of it, should series termination be adequate to limit the
> EMI/EMC problems?
>
> best regards,
> Dolphin
> 

Dolphin wrote:
> Hello,
> 
> In my future design I could win a lot of pins if I could drive a bus at
> 160MHz. Because of bank restrictions and because this bus is connected
> to a CPLD, I will have to use LVTTL.
> Has anybody tried driving a bus in LVTTL at 160MHz?
> 
> I would prefer to use LVDS but the CPLD doesn't allow that. Lattice has
> LVDS CPLDs but only the large CPLDs support LVDS inputs.
> 
> I am afraid that this bus will have a lot of EMI/EMC problems. What do
> you think of it, should series termination be adequate to limit the
> EMI/EMC problems?
> 
> best regards,
> Dolphin
> 
It can be done with extreme care.  Keep the lines short, you may need to 
terminate them, and by all means do a SI simulation on it so that you 
know it will work rather than blindly applying "fixes".

Also be careful of Simulaneously Switching Outputs guidelines. As Ray
says it can be done but if you use a crappy package like PQ208 or TQ144
you may have big problems with ground bounce that causes the interface
to fail. Most of the BGA packages do much better at this fast type of
driving from our experience.

Some CPLDs like the bigger Coolrunner-IIs can also support single ended
standards like SSTL, HSTL that are designed for high speed and may be a
an alternate solution for you. These standards have the advantage of
small signal swings too which is better for ground bounce and EMC.

John Adair
Enterpoint Ltd.

Ray Andraka wrote:
> Dolphin wrote:
> > Hello,
> >
> > In my future design I could win a lot of pins if I could drive a bus at
> > 160MHz. Because of bank restrictions and because this bus is connected
> > to a CPLD, I will have to use LVTTL.
> > Has anybody tried driving a bus in LVTTL at 160MHz?
> >
> > I would prefer to use LVDS but the CPLD doesn't allow that. Lattice has
> > LVDS CPLDs but only the large CPLDs support LVDS inputs.
> >
> > I am afraid that this bus will have a lot of EMI/EMC problems. What do
> > you think of it, should series termination be adequate to limit the
> > EMI/EMC problems?
> >
> > best regards,
> > Dolphin
> >
> It can be done with extreme care.  Keep the lines short, you may need to
> terminate them, and by all means do a SI simulation on it so that you
> know it will work rather than blindly applying "fixes".

Hi,
maybe this is a stupid question, but is there any chance to absorb the 
cpld logic into the FPGA?
this will move your interface inside and make your life easier.
Aurash
Dolphin wrote:

>Hello,
>
>In my future design I could win a lot of pins if I could drive a bus at
>160MHz. Because of bank restrictions and because this bus is connected
>to a CPLD, I will have to use LVTTL.
>Has anybody tried driving a bus in LVTTL at 160MHz?
>
>I would prefer to use LVDS but the CPLD doesn't allow that. Lattice has
>LVDS CPLDs but only the large CPLDs support LVDS inputs.
>
>I am afraid that this bus will have a lot of EMI/EMC problems. What do
>you think of it, should series termination be adequate to limit the
>EMI/EMC problems?
>
>best regards,
>Dolphin
>
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Dolphin wrote:
> Hello,
> 
> In my future design I could win a lot of pins if I could drive a bus at
> 160MHz. Because of bank restrictions and because this bus is connected
> to a CPLD, I will have to use LVTTL.
> Has anybody tried driving a bus in LVTTL at 160MHz?
> 
> I would prefer to use LVDS but the CPLD doesn't allow that. Lattice has
> LVDS CPLDs but only the large CPLDs support LVDS inputs.
> 
> I am afraid that this bus will have a lot of EMI/EMC problems. What do
> you think of it, should series termination be adequate to limit the
> EMI/EMC problems?

You mentioned speed, but forgot distance ?
How far does this have to go - sounds like the CPLD is a (remote?) slave ?
You can get small LVDS-LVTTL transcievers, plus you can also use dual 
data lines, to halve the clock rate. ( see winbond for dual-data SPI 
memory, they spec to 150MHz )
-jg

Add a series-resistor in the lines and/or
use the current-limiting feature of the I/O-ports (if available).
(too reduce the slopes of the signals)

Kind regards,
Stef?

"Dolphin" <Karel.Deprez@gemidis.be> schreef in bericht 
news:1159368842.453549.244660@b28g2000cwb.googlegroups.com...
> Hello,
>
> In my future design I could win a lot of pins if I could drive a bus at
> 160MHz. Because of bank restrictions and because this bus is connected
> to a CPLD, I will have to use LVTTL.
> Has anybody tried driving a bus in LVTTL at 160MHz?
>
> I would prefer to use LVDS but the CPLD doesn't allow that. Lattice has
> LVDS CPLDs but only the large CPLDs support LVDS inputs.
>
> I am afraid that this bus will have a lot of EMI/EMC problems. What do
> you think of it, should series termination be adequate to limit the
> EMI/EMC problems?
>
> best regards,
> Dolphin
>