Hi We are planning to use MIG to generate a DDR2 interface for a V2Pro30 design, but I'd like to know if anyone has done this successfully already? The MIG tool doesn't seem to have the quality level of other Xilinx tools and that makes me a bit nervous for something as timing critical as a DDR2 controller. We are using MIG 007 Rel 6 (as it's the recommended version for V2P). So far the only irritations we have encountered is that it forces the use of specific DCMs and requires the user to reselect every option each time it is invoked (no saving of current design). We plan to run 1 32 bit controller at 200MHz (400 Mb/s/pin) with Micron MT47H16M16. We would like to hear of any experiences with MIG and DDR2 and V2P, if only to convince us that this is doable. Our final design should be open sourced and available to all, if that encourages you to be open about your experiences. If you would rather contact me directly I am at gwatson@stanford.edu Thanks Greg Watson
Anyone had success with MIG, DDR2 and V2Pro?
Started by ●September 27, 2006
Reply by ●September 27, 20062006-09-27
I looked at your Stanford page, what project is this going to be used for? You said that the results will be open sourced, are there any parts of your past projects open? ---Matthew Hicks "Greg Watson" <gwatson@stanford.edu> wrote in message news:efecqi$1m8$1@news.Stanford.EDU...> Hi > > We are planning to use MIG to generate a DDR2 interface for a V2Pro30 > design, but I'd like to know if anyone has done this successfully already? > The MIG tool doesn't seem to have the quality level of other Xilinx tools > and that makes me a bit nervous for something as timing critical as a DDR2 > controller. > > We are using MIG 007 Rel 6 (as it's the recommended version for V2P). So > far the only irritations we have encountered is that it forces the use of > specific DCMs and requires the user to reselect every option each time it > is invoked (no saving of current design). > > We plan to run 1 32 bit controller at 200MHz (400 Mb/s/pin) with Micron > MT47H16M16. > > We would like to hear of any experiences with MIG and DDR2 and V2P, if > only to convince us that this is doable. Our final design should be open > sourced and available to all, if that encourages you to be open about your > experiences. > > If you would rather contact me directly I am at gwatson@stanford.edu > > Thanks > > Greg Watson
Reply by ●September 28, 20062006-09-28
It will be for NetFPGA : http://klamath.stanford.edu/netfpga/ -Greg Matthew Hicks wrote:> I looked at your Stanford page, what project is this going to be used for? > You said that the results will be open sourced, are there any parts of your > past projects open? > > > ---Matthew Hicks > > > "Greg Watson" <gwatson@stanford.edu> wrote in message > news:efecqi$1m8$1@news.Stanford.EDU... >> Hi >> >> We are planning to use MIG to generate a DDR2 interface for a V2Pro30 >> design, but I'd like to know if anyone has done this successfully already? >> The MIG tool doesn't seem to have the quality level of other Xilinx tools >> and that makes me a bit nervous for something as timing critical as a DDR2 >> controller. >> >> We are using MIG 007 Rel 6 (as it's the recommended version for V2P). So >> far the only irritations we have encountered is that it forces the use of >> specific DCMs and requires the user to reselect every option each time it >> is invoked (no saving of current design). >> >> We plan to run 1 32 bit controller at 200MHz (400 Mb/s/pin) with Micron >> MT47H16M16. >> >> We would like to hear of any experiences with MIG and DDR2 and V2P, if >> only to convince us that this is doable. Our final design should be open >> sourced and available to all, if that encourages you to be open about your >> experiences. >> >> If you would rather contact me directly I am at gwatson@stanford.edu >> >> Thanks >> >> Greg Watson > >
Reply by ●October 1, 20062006-10-01
Hi Greg, I would suggest that you might check support.xilinx.com in the Answer database. There are much more topics for DDR than for DDR2. I haven't check all the IO capabilities, however the IO's do not have the same possibilities in Virtex-2P as they have in Virtex-4. For DDR as for DDR2 you need to in deep knowledge if the functionality of the controllers. Use MIG as a starting point for your design, but you need to go through in order to manage all the constraints that come with it, for example IO-placment DCM, global buffers, Fifo's ... etc. You also need to study the generated UCF-File, and check this influences the remaining part of your design. IO-Bank constraints ... For real designs, there is "No-Easy-Path" to DDR2 memory interface designs ... Markus Greg Watson schrieb:> Hi > > We are planning to use MIG to generate a DDR2 interface for a V2Pro30 > design, but I'd like to know if anyone has done this successfully > already? The MIG tool doesn't seem to have the quality level of other > Xilinx tools and that makes me a bit nervous for something as timing > critical as a DDR2 controller. > > We are using MIG 007 Rel 6 (as it's the recommended version for V2P). So > far the only irritations we have encountered is that it forces the use > of specific DCMs and requires the user to reselect every option each > time it is invoked (no saving of current design). > > We plan to run 1 32 bit controller at 200MHz (400 Mb/s/pin) with Micron > MT47H16M16. > > We would like to hear of any experiences with MIG and DDR2 and V2P, if > only to convince us that this is doable. Our final design should be open > sourced and available to all, if that encourages you to be open about > your experiences. > > If you would rather contact me directly I am at gwatson@stanford.edu > > Thanks > > Greg Watson
