Send Ethernet traffic from an FPGA

On Mon, 19 Jan 2004 09:12:42 GMT, "Jean Nicolle"
<j.nicolle@sbcglobal.net> wrote:

>That makes sense.
>Terminating the receiver is just a matter of putting a resistor across the
>wire pair.
>
>Now, the question is, how to terminate the transmitter?
>
>If I assume cat5 cables (100ohms differential impedance?), my first thought
>is to put two 50ohms series resistors on the transmitter side. The downside
>is, it is going to cut in half the incident wave.
>Any better way?

14.3.1.2.2 indicates that the return loss has to be at least 15dB
(between 5.0MHz and 10MHz).

Most approaches for driving terminated lines with good output return
loss will lose half the output power in the driver.  There's not too
much you can do about this if using an FPGA.

You don't say whether the FPGA I/O is powered from 2.5V or 3.3V.  This
makes a difference.

     |
 FPGA|
     |           R1                       .---o
     |           ___               TD+    |   |
     |----------|___|-------. ,-----------'  .-.100 ohm
     |                      )|(              | |test load
     |           ___        )|(    TD-       | |
     |----------|___|-------' '-----------.  '-'
     |                      1:N           |   |
     |           R2                       .---o
     |
     |
     |
created by Andy&#4294967295;s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de 

For best output return loss, (R1 + R2) * N^2 = 100 ohm.
(You should include the output resistance of the FPGA drivers in R1
and R2 - see the IBIS models.)

The (single sided, not peak to peak) output amplitude will be 

Vcc * (100ohm / (100 ohm + (R1 + R2)/N))

E.g. Vcc = 3.3.V,
N = 1 (i.e. it's a 1:1 transformer, a very common type)
then to get the right output amplitude, R1 and R2 will need to be at
most 25 ohms each (including the FPGA output resistance).
This gives an output impedance of 50 ohms though, which is equivalent
to a return loss of only about 9.5dB.

Hmmm.  The only thing to do (apart from violating the specs) is to use
a stepup transformer.  This is actually what most PHYs do (more or
less).

A 1:2 transformer would work well with a Vcc of 2.5V.  R1 and R2 would
still be 25ohm, but the output amplitude would be 2.5V, with a good
return loss.
However, the current in the FPGA output pins would be 50mA.  This
probably isn't practical without using multiple drivers in parallel.

A 1:1.3 transformer would work well with a Vcc of 3.3V.  R1 and R2
would need to be about 30 ohm, and the FPGA output current would come
down to about 32mA.


Note that 14.3.1.2.1 says "[the] transmitter shall provide
equalization such that the output waveform shall fall within the
template shown in Figure 14&#4294967295;9 for all data sequences" 
as well as 
"any harmonic measured on the TD circuit shall be at least 27 dB below
the fundamental."
There is no simple way of providing equalisation when using such a
simple driver.

Regards,
Allan.

Thanks for the *detailed* answer.
I used 3.3V IOs, so I need an 1:1.3 transformer to meet both amplitude and
return loss.
I guess that if I want to use common 1:1 transformers, I need 5V IOs and
50ohms resistors.

For the equalization and harmonic requirements, couldn't I use a filter?
27dB is pretty sharp though, doesn't seem easy.
Looking at some PHY/transformer schematics doesn't show any filter. Is it
usually provided inside the PHY?

Thanks,
Jean

On Tue, 20 Jan 2004 08:52:20 GMT, "Jean Nicolle"
<j.nicolle@sbcglobal.net> wrote:

>Thanks for the *detailed* answer.
>I used 3.3V IOs, so I need an 1:1.3 transformer to meet both amplitude and
>return loss.
>I guess that if I want to use common 1:1 transformers, I need 5V IOs and
>50ohms resistors.

Yes, that would also give a good output level and return loss.  The
FPGA pin current would be 25mA, which would probably be possible
without needing to double-up output drivers.

There is a direct tradeoff between current and voltage at the FPGA
pins which is determined by the transformer ratio.

(ASIC) PHYs often drive into a centre tapped transformer.  The centre
tap is connected to VCC (or sometimes GND).  The outputs only pull
down (one at a time), and the transformer action makes the voltage at
the other output rise above the supply rail.  This allows more voltage
swing from a given supply voltage, but can't be done in an FPGA due to
restrictions in the voltages that can be applied to output pins.  (Or
can it?  You might get lucky with some 5V compliant parts running from
lower voltages.)

>For the equalization and harmonic requirements, couldn't I use a filter?
>27dB is pretty sharp though, doesn't seem easy.

It's not easy.  You'd also need a buffer amp after the filter,
otherwise the line impedance will affect the filter response and it
will also be difficult to get a good (wideband) return loss.

>Looking at some PHY/transformer schematics doesn't show any filter. Is it
>usually provided inside the PHY?

The (FIR) filter is implemented digitally inside the PHY.
You can also think of this as "pulse shaping" rather than filtering.

This sort of thing just isn't feasible inside an FPGA, unless you use
some sort of DAC on the output.  ("Some sort of DAC" could be as
simple as a small number of resistors though.)

This sci.electronics.design thread:
http://groups.google.com/groups?threadm=fntrju0uphuno94gbe0qeue5859v3t5b38%404ax.com
discusses the design of a pulse shaping filter for an ASIC.  The
designer ended up with a combination of an FIR filter (implemented
with a weighted resistor network) inside the ASIC and a single pole LP
filter outside the ASIC to achieve the required pulse shape (and hence
frequency response).

Regards,
Allan.

ok, so the PHY has some analog job to do.
If I make some experiments, I'll look for a solution with a low pin count.
Maybe an R-L filter.
It might be interesting to put all this info available on my site, even if
that's more analog than digital.

In any case, thanks for all this info, I didn't suspect there was so much
analog work involved.
Jean

"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in
message news:a1t110pt27vg5b69uq8vbiopul59eh75o2@4ax.com...
> On Tue, 20 Jan 2004 08:52:20 GMT, "Jean Nicolle"
> <j.nicolle@sbcglobal.net> wrote:
>
> >Thanks for the *detailed* answer.
> >I used 3.3V IOs, so I need an 1:1.3 transformer to meet both amplitude
and
> >return loss.
> >I guess that if I want to use common 1:1 transformers, I need 5V IOs and
> >50ohms resistors.
>
> Yes, that would also give a good output level and return loss.  The
> FPGA pin current would be 25mA, which would probably be possible
> without needing to double-up output drivers.
>
> There is a direct tradeoff between current and voltage at the FPGA
> pins which is determined by the transformer ratio.
>
> (ASIC) PHYs often drive into a centre tapped transformer.  The centre
> tap is connected to VCC (or sometimes GND).  The outputs only pull
> down (one at a time), and the transformer action makes the voltage at
> the other output rise above the supply rail.  This allows more voltage
> swing from a given supply voltage, but can't be done in an FPGA due to
> restrictions in the voltages that can be applied to output pins.  (Or
> can it?  You might get lucky with some 5V compliant parts running from
> lower voltages.)
>
> >For the equalization and harmonic requirements, couldn't I use a filter?
> >27dB is pretty sharp though, doesn't seem easy.
>
> It's not easy.  You'd also need a buffer amp after the filter,
> otherwise the line impedance will affect the filter response and it
> will also be difficult to get a good (wideband) return loss.
>
> >Looking at some PHY/transformer schematics doesn't show any filter. Is it
> >usually provided inside the PHY?
>
> The (FIR) filter is implemented digitally inside the PHY.
> You can also think of this as "pulse shaping" rather than filtering.
>
> This sort of thing just isn't feasible inside an FPGA, unless you use
> some sort of DAC on the output.  ("Some sort of DAC" could be as
> simple as a small number of resistors though.)
>
> This sci.electronics.design thread:
>
http://groups.google.com/groups?threadm=fntrju0uphuno94gbe0qeue5859v3t5b38%404ax.com
> discusses the design of a pulse shaping filter for an ASIC.  The
> designer ended up with a combination of an FIR filter (implemented
> with a weighted resistor network) inside the ASIC and a single pole LP
> filter outside the ASIC to achieve the required pulse shape (and hence
> frequency response).
>
> Regards,
> Allan.