LVDS termination scheme to nonstandard ribbon cable

Symon wrote:
> However, I share Brian's frustration when it's implied that the Cpin is a 
> 'good thing' because, for example, "cross talk is reduced". Not powering the 
> part is another way to reduce crosstalk, and only a little less practical.

:)

> 
> http://sigcon.com/Pubs/edn/TerminatorOne.htm  (Look at the figure, is he 
> timing 8ns with an egg timer? :-)

Yup, the original 'silicon chips' timer ;)

-jg

John_H wrote:
>
>Since the transmitters will tend to have high C as well
> in Xilinx transmitters, reflections should be expected.
>
 FPGA driving FPGA, or FPGA driving non-FPGA, are usually
much easier to deal with.

 My posts cautioning about Cin have always been in the context
of a fast, non-FPGA driver (LVDS, LVDS-ish, ECL, etc. ) into
a FPGA input with big Cin.

 When the thread discussion turned to external matching
networks for ECL drivers, I thought the T-coil Cin
matching scheme would be of interest.

>
> One thing you appear to rely on from previous posts is probing
> of the signal at a point external to the receiver silicon, the
> only place practical to probe.  This will always result in a
> signal that's worse than the actual received signal when high
> Cs (or other impedance mismatches) are involved.
> <snip>
>   The SI results will often provide much better response than your
> practical observations.
>
 I use lab measurements to verify my simple first or second
order SPICE simulation models at the points I CAN observe,
after which I can then experiment in simulation with some
comfort of reality being conserved at the receiver input.

 I 'forward' clock and test signals on/off chip using
LVDS DIFF_OUT buffers and OFDDR's, letting me measure
clock distribution without the need for a DCM.

 A mechanical trombone line allows an internal sample clock
to be offset without any need to worry about DCM jitter or
other on-chip delay techniques.

 Tek probes of 15-20 years ago in the form of an SD-14
or P6150 (with bias offset), on an 1180x or CSA803 sampler,
can easily measure 1 Gbps LVDS, with minimal loading impact,
and are practically free since the dot com telecom bust.

 Note that sometimes my use of the word "probe" is intended in
the context of "bus probe", in which case the external probe
is capturing and analyzing the bus traffic- this requires the
reflections be damped or otherwise equalized at the point
of probe attachment so that the sample clock is usable.

>
> It really is C/2 for those who are thinking 100 ohm impedance.
> It really is C for those who are thinking 50 ohm impedance.
> Where are peoples' minds normally on the impedance for LVDS?
> There are no lies here.
>
 When I say "10 pf Cin (single ended)", I am specifically
referencing Xilinx's only datasheet spec for capacitance,
called Cin, which is a single-ended specification.

 I have pointed this out to Austin numerous times, yet he
still insists on "correcting" ( his term ) any references
to Xilinx's published Cin values, even after I started
explicitly postfixing the '(single ended)' whenever I
reference Cin.

 My references to C_COMP and C_PKG are also, like their
IBIS values, single ended.

 I am loath to quote the calculation Cin/2 instead of the
actual specification values because :

  1) It's only valid if the input is perfectly differential

  2) A more realistic input model includes pin-pin capacitance
   separately as Cdiff, giving a calculated total differential
   capacitance Ccalc = Cdiff + Cin/2

 IIRC, one of the IBIS summit papers discussed LVDS modeling
using a C_DIFF, C_PKG, and C_IN, but I can't turn up the
paper just now.

>
> I love that a 600 Mbit link in the "cheap" S3E devices
> hampered not by one but by TWO DCMs can result in an eye
> that's still half open; I could blame just about all of
> that mess on the DCMs, not the LVDS transceivers.
>
 I also think the S3E's are great.

 C_PKG + C_COMP ~= 3 pf,  $$ < 10, at quantity 1 in VQ100

Brian

Some additions to John's advice, assuming we are talking
of an original S3 family device ( not E,A,AN,... )

John_H wrote:
>
> The receiver should be the differential impedance of the cable and of
> the transmitter - they should all (roughly) match.  If you have an
> external termination at the receiver, change it to the 173 ohm value if
> that's the true differential impedance.  If the termination is internal
> at 100 ohms, add two 36 ohm resistors (or thereabouts) to get the
> impedance match, albeit at a reduced signal amplitude.
>

 If this is an original Spartan-3, the differential terminations
are not available, so external terminations will be needed.

 Put them as close to the package as you can, especially for any
clock or strobe signals.

>
> On the transmitter, you want a 100 ohm to 173 ohm impedance match so the
> transmitter sees 100 ohm but the transmission line sees 173 ohm.  You'll
> need a differential termination on the transmitter side of this network
> and two series resistors to the ribbon cable.  The signal amplitude will
> again be reduced.
>

 Here, I'd suggest a switch to the LDT output standard instead
of LVDS, which will give you higher minimum drive and will help
make up for the lower output amplitude caused by the series
matching resistors.

 I'd normally suggest using LVDS_EXT, another variant of LVDS
with extra drive, but in the original S3, the differential
output specs are a bit odd, with Vod(min) of only 100 mV for
both LVDS and LVDS_EXT, unless you have a certain mask revision.
( See table 37 of DS099 v2.2 )

 As you are going FPGA to FPGA, you can switch the I/O standards
on both ends, but watch the change in SSO limits for the various
differential standards ( See table 49 of DS099 v2.2 )

Brian