Quartus-II 7.1 Systemverilog support define `` ?

Does Quartus-II 7.1 support the Systemverilog preprocessor's `` 
concatenator?

`define pori_reg(r) \
  r <= def_``r

localparam int def_hp_length = 800;
localparam int def_hp_retrace_end = 720;
localparam int def_hp_disp_start = 80;

always @( posedge clk )
if ( !rstn )
  begin
    `pori_reg( hp_length        );
    `pori_reg( hp_retrace_end   );
    `pori_reg( hp_disp_start    );

/////////////////////////////////////////////////
// equivalent to
/////////////////////////////////////////////////

always @( posedge clk )
if ( !rstn )
  begin
    hp_length <= def_hp_length;
    hp_retrace_end <= def_hp_retrace_end;
    hp_disp_start <= def_hp_disp_start;

This simulates fine in Modelsim XE-III 6.2c Starter Edition, but Quartus 
complains:
Error (10108): Verilog HDL Compiler Directive error at vga_reg.sv(42): 
missing Compiler Directive
Error (10170): Verilog HDL syntax error at vga_reg.sv(42) near text 
"hp_length";  expecting ";"
... 

On May 27, 10:12 pm, "Xilinx user" <xilinx_u...@nowhere.net> wrote:
> DoesQuartus-II 7.1 support theSystemverilogpreprocessor's ``
> concatenator?
>
> `define pori_reg(r) \
>   r <= def_``r
>
> localparam int def_hp_length = 800;
> localparam int def_hp_retrace_end = 720;
> localparam int def_hp_disp_start = 80;
>
> always @( posedge clk )
> if ( !rstn )
>   begin
>     `pori_reg( hp_length        );
>     `pori_reg( hp_retrace_end   );
>     `pori_reg( hp_disp_start    );
>
> /////////////////////////////////////////////////
> // equivalent to
> /////////////////////////////////////////////////
>
> always @( posedge clk )
> if ( !rstn )
>   begin
>     hp_length <= def_hp_length;
>     hp_retrace_end <= def_hp_retrace_end;
>     hp_disp_start <= def_hp_disp_start;
>
> This simulates fine in Modelsim XE-III 6.2c Starter Edition, butQuartus
> complains:
> Error (10108): Verilog HDL Compiler Directive error at vga_reg.sv(42):
> missing Compiler Directive
> Error (10170): Verilog HDL syntax error at vga_reg.sv(42) near text
> "hp_length";  expecting ";"
> ...

No, Quartus II does not support any of the `define extensions defined
by the SystemVerilog language.  These include `", `\`", and ``.  These
features will be added to Quartus II 8.0.

- Subroto Datta
Altera Corp.

Thank you!

Will Quartus-II 8.0 support unnamed-block variable-declarations?
(The example below causes syntax-error in Quartus-II 7.1 April 2007.)

always_comb begin
  for ( int i = 0; i < 256; ++i )
     my_array[i] = in_a[i] + in_b[i];
end

"Subroto Datta" <sdatta@altera.com> wrote in message 
news:1180985053.020785.303430@a26g2000pre.googlegroups.com...
> On May 27, 10:12 pm, "Xilinx user" <xilinx_u...@nowhere.net> wrote:
>> DoesQuartus-II 7.1 support theSystemverilogpreprocessor's ``
>> concatenator?
>>
>> `define pori_reg(r) \
>>   r <= def_``r
>> ...
>
> No, Quartus II does not support any of the `define extensions defined
> by the SystemVerilog language.  These include `", `\`", and ``.  These
> features will be added to Quartus II 8.0.
>
> - Subroto Datta
> Altera Corp.
>
>