Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim

Austin,

How accurate is the timing for post place and route simulations using the 
Xilinx libraries?


---Matthew Hicks


> Craig,
> 
> Depending on what tools you used to capture the schematic, and what
> models your flow supports, asking for a "verilog netlist" is a feature
> of some tools.
> 
> The resulting verilog netlist will be at the transistor and wire
> level, or gate level (which in the hierarchy is made up of gates and
> wires), and will basically allow you to functionally simulate the
> schematic, less any timing, or 'analog' behavior (after all, you only
> have 1's, 0's, 'don't cares', tri-states, and unknowns).
> 
> This is commonly done for ASIC/ASSP design:  one may synthesize higher
> level RTL (like verilog and VHDL descriptions that have no specific
> technology or functional modules like 'multiply this by that') into
> lower level schematics of transistors (from standard cell library
> gates).
> 
> The resulting circuit netlist (like a spice netlist) will allow one to
> perform many good (analog) simulations, but will either take too long,
> or blow up, if there are close to a billion devices in the chip.  The
> next choice is to simulate the verilog netlist of the wires and
> transistors, which will run much much faster, but will be unable to
> tell you anything about time, voltage, or current.
> 
> Since you posted on c.a.f. I am going to presume your HDL was
> synthesized for a FPGA, and then it was placed, and routed in the
> FPGA.
> 
> You may also have a schematic of how the HDL blocks are connected
> together.  The resultant netlist is in some format (for Xilinx: XDL)
> which may then be simulated quickly for the functional behavior.
> 
> In an FPGA, the translation all the way down to transistors is not
> provided, like it would be in the ASIC/ASSP flow....
> 
> Make sense?
> 
> Austin
> 

Matthew,

We stand by the speeds files.  In other words, if the actual part is
slower, on any path or feature, it may be returned (via the RMA
process), and we issue a new one that meets the specifications.

I have taken part in many such cases, and on only two occasions, we had
made a mistake in the speeds file, and we had to offer a faster speed
grade part to the customer, or work with them to improve their timing to
get around the failing path.

It is so extremely painful to have to issue a new (slower) speeds file
for our customers; we only do that when we have no other alternative
whatsoever (and you can believe we get hammered internally for having
the wrong number in the speeds file).

The same is true for IBIS models, packaging files, etc.

Austin

Sorry I'm trying to be very practical here. I just want to know what
command line tools I can use to create a verilog file from a schematic
file.

How do I do that from the command line using either ISE 9.1i or
ModelSim?

I'd appreciate it if you could give me an example?

Lets say my schematic is named: circuit.sch

I'd like to create a verilog file (netlist) that is equivilent to it,
say: circuit.v

I'm guessing at the command line it would be something like:

xst -sch circuit.sch > circuit.v

I have read through all the user manuals, developer manuals, etc... I
can't not figure out how to do this outside of the GUI interface.

Thanks again for any help you can provide.

Thanks,
Craig.

Craig,

I must apologize, because I am an IC designer, not really a FPGA user (I
mostly use very simple and straightforward designs to verify the blocks,
and rely on others to write the systems level stuff).

I am also not a software expert.

There are Xilinx employees who read this newsgroup from our software
group, however.

If they do not respond, I am going to have to assume we can not do what
you ask with our tools.

Austin

Craig Moore wrote:
> Sorry I'm trying to be very practical here. I just want to know what
> command line tools I can use to create a verilog file from a schematic
> file.
> 
> How do I do that from the command line using either ISE 9.1i or
> ModelSim?
> 
> I'd appreciate it if you could give me an example?
> 
> Lets say my schematic is named: circuit.sch
> 
> I'd like to create a verilog file (netlist) that is equivilent to it,
> say: circuit.v
> 
> I'm guessing at the command line it would be something like:
> 
> xst -sch circuit.sch > circuit.v
> 
> I have read through all the user manuals, developer manuals, etc... I
> can't not figure out how to do this outside of the GUI interface.
> 
> Thanks again for any help you can provide.
> 
> Thanks,
> Craig.
>