I've figured out how to compile the RTL in Xilinx ISE Webpack9.2i and Altera Quurtus II 7.1. (It just took a few simple RTL-edits.) But what about the JTAG-debug unit? It seems to use the Lattice's JTAG-block. Can I just replace this with a generic JTAG TAP-controller, and then use a Xilinx-hosted Mico32 with a Lattice download-cable?
How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?
Started by ●July 18, 2007
Reply by ●July 19, 20072007-07-19
On 18 Jul., 07:55, "Ssa" <s...@djfs.com> wrote:> I've figured out how to compile the RTL in Xilinx ISE Webpack9.2i and Altera > Quurtus II 7.1. (It just took a few simple RTL-edits.) > > But what about the JTAG-debug unit? It seems to use the Lattice's > JTAG-block. > Can I just replace this with a generic JTAG TAP-controller, and then use a > Xilinx-hosted Mico32 with a Lattice download-cable?if you rebuild the lattice jtag-tap then yes. but you have to use fpga regular io pads, not xilinx bscan antti