JTAG + PROM error!

Hi,

I have the problem that I can't communicate with my Xilinx XCF04S PROM
through JTAG. The circuit setup is a "3.3V Master-Serial Configuration
with 3.3V and JTAG with Platform Flash Prom" as here:
http://www.xilinx.com/support/answers/20477.htm. To reduce the sources
of error, I disconnected the JTAG input signals TMS, TCK, TDO to the
FPGA, and connected the TDO directly from the PROM to the connector,
therefore bypassing the FPGA. According to the PROM datasheet, the
only pins that matters additionaly to the JTAG signals is the #CE pin
(this pin is always low) and power pins.
I checked with an oscillator the JTAG signals:

TCK
http://img165.imageshack.us/my.php?image=jtagtcktes1hl8.png

TDI
http://img81.imageshack.us/my.php?image=jtagtdites1db4.png

TDO
http://img341.imageshack.us/my.php?image=jtagtdotes1fi0.png

TMS
http://img341.imageshack.us/my.php?image=jtagtmstes1io0.png

All JTAG signals toggel (i measured on the IC and connector to exclude
any soldering problems). I noticed that TDI and TCK look very similar,
however there is not short-cut between them

When I do an ID Check, i get this:

INFO:iMPACT:1578 - '1':  Device IDCODE :
00001111111111111111111111111111
INFO:iMPACT:1579 - '1': Expected IDCODE:
00000101000001000110000010010011


I would like to have your opinions what you think the error is?


Thank you,
Jidan

I think the the problem lays on the TDO signal. The rising edge on TDO
is abnormally slow and flat on the first pulse, here:
http://img239.imageshack.us/my.php?image=jtagtdoprommh2.png . The TDO
signal is connected directly from PROM to a Xilinx JTAG USB cable.
Does somebody know why the signal is so flat?



Thanks,

JJ

On Jun 5, 6:10 am, jid...@hotmail.com wrote:
> I think the the problem lays on the TDO signal. The rising edge on TDO
> is abnormally slow and flat on the first pulse, here:http://img239.imageshack.us/my.php?image=jtagtdoprommh2.png. The TDO
> signal is connected directly from PROM to a Xilinx JTAG USB cable.
> Does somebody know why the signal is so flat?
>
> Thanks,
>
> JJ

Any chance that the power was still coming up when you acquired the
trace on your 'scope?

On 5 Jun., 14:57, Gabor <ga...@alacron.com> wrote:
> On Jun 5, 6:10 am, jid...@hotmail.com wrote:
>
> > I think the the problem lays on the TDO signal. The rising edge on TDO
> > is abnormally slow and flat on the first pulse, here:http://img239.imageshack.us/my.php?image=jtagtdoprommh2.png. The TDO
> > signal is connected directly from PROM to a Xilinx JTAG USB cable.
> > Does somebody know why the signal is so flat?
>
> > Thanks,
>
> > JJ
>
> Any chance that the power was still coming up when you acquired the
> trace on your 'scope?

No, that wasnt the case.
I found out something interesting. When I touch the TDO signal with
the oscillscope probe, the ID check and programming works!!!! And I
think the probe induced a small parallel capacitance to GND that made
this work. I have never found anything on this on xilinx application
notes. The question is now what capacitance value is the best?

JJ

> No, that wasnt the case.
> I found out something interesting. When I touch the TDO signal with
> the oscillscope probe, the ID check and programming works!!!! And I
> think the probe induced a small parallel capacitance to GND that made
> this work. I have never found anything on this on xilinx application
> notes. The question is now what capacitance value is the best?
>
> JJ

	I don't know if that's going to help but I literally spent days on making  
the JTAG work and :

http://audio.peufeu.com/node/68

	This was after going through 3 flat cables which actually ALL were  
defective, lol. The 4th cable is starting to die, too. Sometimes I have to  
fold it just the right way to make contact. I need to get some more  
connectors. There must be some curse on those.

	Also if you see funky waveforms on TDO this may be because when the  
chip's JTAG is idle, its output is tristated, but when it's active, its  
output is actively driving the cable. So, when it switches from active  
drive to tristate, it leaves only the pullup trying to fight with the  
cable capacitance. Hence you can see those waveforms on the scope. I don't  
think it's a problem though.

	Xilinx oh Xilinx please put schmitt triggers on the TCK input...

> No, that wasnt the case.
> I found out something interesting. When I touch the TDO signal with
> the oscillscope probe, the ID check and programming works!!!! And I
> think the probe induced a small parallel capacitance to GND that made
> this work. I have never found anything on this on xilinx application
> notes. The question is now what capacitance value is the best?

	Oh yeah I forgot : last time this happened to me it was because the  
pressure I exerted while probing did restore the contact in the faulty  
flat cable connector...

On 6 Jun., 14:42, PFC <li...@peufeu.com> wrote:
> > No, that wasnt the case.
> > I found out something interesting. When I touch the TDO signal with
> > the oscillscope probe, the ID check and programming works!!!! And I
> > think the probe induced a small parallel capacitance to GND that made
> > this work. I have never found anything on this on xilinx application
> > notes. The question is now what capacitance value is the best?
>
>         Oh yeah I forgot : last time this happened to me it was because the
> pressure I exerted while probing did restore the contact in the faulty
> flat cable connector...

Thanks for the feedback. But in my case it was definatly the
capacitor. I added a 100pF from GND to TDO on the JTAG programmer side
and it worked. The cable is less than 30 cm and the frequency is 3/6
MHz. The JTAG programmer or Xilinx FPGA must be really sensitive.

On 6 Jun., 15:29, jid...@hotmail.com wrote:
> On 6 Jun., 14:42, PFC <li...@peufeu.com> wrote:
>
> > > No, that wasnt the case.
> > > I found out something interesting. When I touch the TDO signal with
> > > the oscillscope probe, the ID check and programming works!!!! And I
> > > think the probe induced a small parallel capacitance to GND that made
> > > this work. I have never found anything on this on xilinx application
> > > notes. The question is now what capacitance value is the best?
>
> >         Oh yeah I forgot : last time this happened to me it was because the
> > pressure I exerted while probing did restore the contact in the faulty
> > flat cable connector...
>
> Thanks for the feedback. But in my case it was definatly the
> capacitor. I added a 100pF from GND to TDO on the JTAG programmer side
> and it worked. The cable is less than 30 cm and the frequency is 3/6
> MHz. The JTAG programmer or Xilinx FPGA must be really sensitive.

What I want to understand, is why only the TDO signal?
And if 30 cm was long or the cable was bad quality, then why didnt I
see any distortions on the signals coming from the JTAG programmer?