Using ethernet on a Xilnx board (Help appreciated)

Pat,
I am learning Verilog as well, my guess is that you may not handle correcly 
NLP/FLP stuff, that's the reason the interface seems down.

Take a look here:

http://www.fpga4fun.com/10BASE-T0.html

"Keeping the link alive
Even if no packets are sent on a 10BASE-T cable, a pulse has to be sent 
periodically (called the "Normal Link Pulse" or "NLP"). It is used to keep 
the connection "alive". A pulse needs to be sent every 16ms or so.

The NLP can also be replaced by a "Fast Link Pulse" (FLP) burst, during a 
process called "auto-negotiation". The FLP carries information about the 
capabilities of the sender, so that the hardware at both end of a cable can 
negotiate the link parameters, like the speed and the half/full duplex 
status."

Giuseppe Marullo

giuseppe.marullo.nospam@iname.com