TI DSP + Virtex-5 using EMIF interface

Hi all,
I'm working on a realtime application that requires to elaborate a
digital video stream 25fps. Algorithms are very time consuming and an
hardware parallel solution can help to satisfy time constraints.

Finally I decided for a mixed SW and HW that consists in a TI DSP and
a Virtex-5 connected togheter on EMIF.

Initially I choosed a Virtex-5SX, because it has a large number of DSP
blocks and a good number of logic cells (usefull for parallel hardware
implementations), but on the net I saw that people tend to use
Virtex-4FX as co-processor for TI DSP. I suppose that this choice is
strictly related to the presence of an hard core PowerPC on
Virtex-4FX, but I'm not sure.

In addition I didn't found any reference design for EMIF interface in
Virtex-5 (there are only for Virtex-4 or Virtex-II). Could be this a
good reason to choose a Virtex-4 instead of Virtex-5?

The V4 is thant the V5 older, so it is only natural that there are
more published designs for it.
The EMIF is a rather generic bus interface, very similar to dozens of
other CPU or SRAM interfaces.
There is nothing specific about it that affects FPGA choice. You
probably can use V4 HDL code for
an EMIF interface without modifications in an V5.

Also: If you can't code the interface yourself you probably should not
start this project. The EMIF
interface is not more complicated than what you would use internally
to interface to the components
of your design. Using existing code therefore provides next to no
abstraction.

Did you see XAPP573?

The circuits to interface to a FIFO inside the FPGA are not much more
than half a dozen gates.

Kolja Sulimma


On 9 Jun., 11:24, techG <giuliopul...@gmail.com> wrote:
> Hi all,
> I'm working on a realtime application that requires to elaborate a
> digital video stream 25fps. Algorithms are very time consuming and an
> hardware parallel solution can help to satisfy time constraints.
>
> Finally I decided for a mixed SW and HW that consists in a TI DSP and
> a Virtex-5 connected togheter on EMIF.
>
> Initially I choosed a Virtex-5SX, because it has a large number of DSP
> blocks and a good number of logic cells (usefull for parallel hardware
> implementations), but on the net I saw that people tend to use
> Virtex-4FX as co-processor for TI DSP. I suppose that this choice is

> strictly related to the presence of an hard core PowerPC on
> Virtex-4FX, but I'm not sure.
>
> In addition I didn't found any reference design for EMIF interface in
> Virtex-5 (there are only for Virtex-4 or Virtex-II). Could be this a
> good reason to choose a Virtex-4 instead of Virtex-5?

On Jun 9, 3:08 pm, Kolja Sulimma <ksuli...@googlemail.com> wrote:
> The V4 is thant the V5 older, so it is only natural that there are
> more published designs for it.
> The EMIF is a rather generic bus interface, very similar to dozens of
> other CPU or SRAM interfaces.
> There is nothing specific about it that affects FPGA choice. You
> probably can use V4 HDL code for
> an EMIF interface without modifications in an V5.
>
> Also: If you can't code the interface yourself you probably should not
> start this project. The EMIF
> interface is not more complicated than what you would use internally
> to interface to the components
> of your design. Using existing code therefore provides next to no
> abstraction.
>
> Did you see XAPP573?
>
> The circuits to interface to a FIFO inside the FPGA are not much more
> than half a dozen gates.
>
> Kolja Sulimma
>
> On 9 Jun., 11:24, techG <giuliopul...@gmail.com> wrote:
>
> > Hi all,
> > I'm working on a realtime application that requires to elaborate a
> > digital video stream 25fps. Algorithms are very time consuming and an
> > hardware parallel solution can help to satisfy time constraints.
>
> > Finally I decided for a mixed SW and HW that consists in a TI DSP and
> > a Virtex-5 connected togheter on EMIF.
>
> > Initially I choosed a Virtex-5SX, because it has a large number of DSP
> > blocks and a good number of logic cells (usefull for parallel hardware
> > implementations), but on the net I saw that people tend to use
> > Virtex-4FX as co-processor for TI DSP. I suppose that this choice is
> > strictly related to the presence of an hard core PowerPC on
> > Virtex-4FX, but I'm not sure.
>
> > In addition I didn't found any reference design for EMIF interface in
> > Virtex-5 (there are only for Virtex-4 or Virtex-II). Could be this a
> > good reason to choose a Virtex-4 instead of Virtex-5?


Hi,
I think that the interface speed of EMIF can be defined based on the
distance between the processor and FPGA chip. While attempting to
capture 30-Frames per second from Camera link interface, I interfaced
TI- C-64x processor with XC2V1000 FPGA via 64-bit asynchronous EMIF
interface at 133Mhz (internal clock) with processor setup and strobe
set to one cycle when the physical distance between the chips was
about one inch; and the same interface slowed by approximately five
times when the distance increased to two inches.

Important thing is to avoid setup and hold uncertainties and sample
data at right time. Use DCMs and phase shifted clocks to sample at
right time and the only limiting factor in the speed of the interface
was the speed of block RAM that could not run at a speed above 120MHz
in Virtex-2.

30-FPS can easily be done in Vitex2/ Spartan series FPGAs, I think
virtex-4/5 would allow much more than that.

Hope this helps

Regards
/MH