Xilinx/Altera gate equivalence

On Wed, 16 Jul 2008 17:20:10 -0700 (PDT), dudesinmexico
<dudesinmexico@gmail.com> wrote:

>On Jul 16, 3:15&#4294967295;pm, austin <aus...@xilinx.com> wrote:
>> dudes,
>>
>> If you contact your Xilinx FAE I am sure they would be happy to help you.
>>
>
>So these days Xilinx FAEs help their customers to port their designs
>to Altera?
>Sorry Austin, I could not resist.. ;)

maybe he means "help" as in "set you right about such a silly idea" :-)
or, being optimistic, ... maybe he means, provide a discounted price to
keep you with Brand X?

- Brian

There is a comparision done by Altera between Stratix III an Virtex-5

http://www.altera.com/products/devices/stratix-fpgas/stratix-iii/overview/architecture/performance/st3-opencores.html

Maybe I missed it, maybe it is not mentioned, but I cannot find the 
HDL-compiler used and its settings thus the results might vary and You 
should not fully rely on a vendor's result (especially if the vendor 
wins against his competitor in the result).

But there You will find a technical description on how to perform such a 
test-case. This possibly might help.

Regards,

Lorenz

Lorenz Kolb <lorenz.kolb@uni-ulm.de> wrote:

>Bert wrote:
>> On 17 jul, 05:00, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal
>> Murray) wrote:
>>>> Anyway, this is not an academic exercise. Porting a very complex
>>>> Virtex4 design
>>>> to Stratix is not something that one can do in a few days, so I was
>>>> looking
>>>> for ballpark estimates about the equivalence between Xilinx and Altera
>>>> "gates".
>>> Have you looked at the Stratix data sheet?  Did you find anything
>>> close to a CLB/FF pair?  If so, assume they are 1:1.
>>>
>>> Then count the special things you use: BRAMs, clock buffers, multipliers
>>> and whatevber.  Then see if Altera has something similar.
>>>
>>> --
>>> These are my opinions, not necessarily my employer's.  I hate spam.
>> 
>> Hi,
>> 
>> I have searched before about the comparison Logic Elements and Logic
>> Cells. Most of the result say LE = LC, but once (@ Altera website) I
>> found that LE = 1.125*LC
>> 
>> Bye
>> Bert
>
>This highly depends on the actual design, there are some minor 
>differences between LEs and LCs that might or might not have an 
>advantage for certain designs. Nevertheless estimating 1:1 is a fairly 
>good choice in my opinion. At least as long as you do not want to go 
>without any reserve of LEs/LCs.


I don't think so. I guess the best estimate is to determine the amount
of flipflops in use in both normal flipflops and LUT ram. You'll need
an Altera device with at least that amount of flipflops. Next thing
you'll need to compare blockrams, multipliers, etc. But the latter is
relatively easy.

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