Strange Spartan2 behaviour

Jochen <JFrensch@harmanbecker.com> wrote:

>On 4 Sep., 18:06, n...@puntnl.niks (Nico Coesel) wrote:
>> Jochen <JFren...@harmanbecker.com> wrote:
>> >We had an issue with a "ground bounce" (Spartan3 design) in the bank
>> >containing the PCI-interface, which 'triggered' the asynchonous reset
>> >of the PCI-core...
>>
>> >Do you use async resets ?
>>
>> Yes. The design uses async resets. But it doesn't seem to affect the
>> PCI core. The problem is always in the part with the statemachines.
>>
>
>well - let's have a look at
>     http://forums.xilinx.com/xlnx/blog/article?message.uid=12856
>
>esp. chapter "Unreliable Sporadic Behaviour!"

Interesting reading material. Thanks. Meanwhile I removed all async
resets from the design. I'm still waiting for the test results though.
The silly thing is that the Xilinx PCI core examples the design is
based upon are full of async resets.

>P.S.
>   Ken really knows, what he is talking about !!!

No doubt about that!

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