CASCADING DCM

Hi 
   I would like to take the CLK2X output of DCM and give it to the
CLKIN pin of 2(TWO) DCM'S.Is it possible to do so. Does this result in
more jitter.

regards 
vivek

I tried once, cascading did not function in simulation. 2nd DCM complained
the jitter
of its input clock being higher than 1ns. Why not just use CLKFX instead of
X2X2...

Kelvin




"vivek" <vivek_vt@hotmail.com> wrote in message
news:e139d08b.0403020140.28fd83c8@posting.google.com...
> Hi
>    I would like to take the CLK2X output of DCM and give it to the
> CLKIN pin of 2(TWO) DCM'S.Is it possible to do so. Does this result in
> more jitter.
>
> regards
> vivek

I recently wrote a tutorial description of the Xilinx DCM features and
limitations. It's a bit long, but it might help some people in this newsgroup:

Xilinx DCMs
This is a description of the capabilities and the limiatations of all
Xilinx Digital Clock Manager (DCM) circuits. 
 
Basic functionality:
In its simplest use, the DCM  eliminates the clock delay between the
incoming clock signal and the low-skew global clock distribution. With
the appropriate feedback to its CLKFB input the DCM  inserts the right
amount of delay so that CLKIN and CLKO signals occur simultaneously
(within a very small fraction of a nanosecond). Physically, CLKO is
delayed by exactly one clock period, and this obviously requires a
free-running, constant-frequency CLKIN.

In BASE mode the incoming clock frequency can be multiplied by any
integer from 1 to 32, or the clock frequency can be divided by any
integer from 2 to 16, as well as divided by the non-integer values of
1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5. The output is edge-aligned with
the rising CLKIN edge whenever that is mathematically possible. (When
divided by x.5, only every other output edge is aligned with the input
edge). For integer multiply and divide ratios, the output is
automatically adjusted to a 50% duty cycle. 
In BASE mode, the max frequency limit aplies to input and output
frequencies, but the min frequency limit of 24 MHz applies only to the
input frequency.

In Frequency Synthesis mode,the incoming clock frequency can be
simultaneously multiplied and divided by any integer from 1 through 32.
A 200 MHz input, for example, can be multiplied by 19 and divided by 20
to generate a 190 MHz output. Since multiplication and division are
performed mathematically, no 3.8 GHz internal frequency is generated. In
FS mode, the max frequency limit aplies to input and output
frequencyies, but the min frequency limit of 24 MHz applies only to the
output (!) frequency.  

Note the difference: 
In BASE mode it's the input frequency that must be above 24 MHz, 
in FS mode it's the output frequency.

Practical examples in BASE mode: 
26 MHz : 13 =  2.0 MHz,  
250 MHz : 2.5 = 100 MHz,  
50 MHz x 5 = 250 MHz

Practical examples in Frequency Synthesis mode:
10 MHz x 31 : 5 =  62 MHz      
200 MHz x 27 : 20 = 270 MHz

Not possible:
20 MHz : 5 = 4 MHz 
( input frequency is too low for BASE mode, and output frequency is too
low for FS mode. Use flip-flop dividers instead)

7 MHz x 6 : 5 = 8.4 MHz 
(output frequency is too low, change to  
7MHz x 24 : 5 = 33.6 MHz 
and use two flip-flops to divide by the output by 4.) 

The flip-flops can then drive the global clock buffer, but do not
guarantee the tight delay specification offered by the DCM. Note however
that phase coherence in FS mode obviously can occur only once every D
input cycles = once every M output cycles, and usually is irrelevant in
a real application.

Input Jitter:
The DCM  is guaranteed to tolerate max 1 ns of cycle to cycle jitter on
its input. Higher jitter can cause the DCM  to loose lock, which is then
indicated on the Lock output going High, or the CLKFX_Stopped bit going High.

Output jitter:
Use the software tools to calculate the output jitter. There are
additional software tools available to evaluate the effect of M and D on
the output jitter. Contact your FAE..

Phase Shift Operation:
The DCM  can provide phase-shifted outputs. 

In BASE mode, it provides the input frequency with four phase angles (
0, 90, 180, and 270 degrees), as well a the double frequency and the
double frequency inverted (180 degr)

In Phase Shifted (PS) mode, all outputs are shifted by a common amount,
defined by an 8-bit control word N that specifies the phase shift of
N/256 times the incoming clock period. The granularity is also limited
by the delay chain increments, roughly 30 ps. This determines the
effective resolution for frequencies above 150 MHz. 
The user can specify any one of 256 values, and the DCM will make the
closest possible approximation, within 30 ps. 
The value N is usually set by configuration, but can also be adjusted
dynamically during operation.

I hope this long posting is helpful.
Peter Alfke, Xilinx Applications

Peter Alfke wrote:
> I recently wrote a tutorial description of the Xilinx DCM features and
> limitations. It's a bit long, but it might help some people in this newsgroup:
> 
> Xilinx DCMs
> This is a description of the capabilities and the limiatations of all
> Xilinx Digital Clock Manager (DCM) circuits. 
>  
> Basic functionality:
> In its simplest use, the DCM  eliminates the clock delay between the
> incoming clock signal and the low-skew global clock distribution. With
> the appropriate feedback to its CLKFB input the DCM  inserts the right
> amount of delay so that CLKIN and CLKO signals occur simultaneously
> (within a very small fraction of a nanosecond). Physically, CLKO is
> delayed by exactly one clock period, and this obviously requires a
> free-running, constant-frequency CLKIN.

Isn't it CLKIN and CLKFB that occurs simultaniously? A typical example 
is if you use the DCM for of chip de-skewing. In this case you would 
like a certain point of the net on the PCB to be phase aligned with 
CLKIN. This requires that the CLK0 path to this point and the FB path 
from this point back to the DCM are matched. When the CLKFB and CLKIN 
are in phase this specific point will be phase aligned with CLKIN but 
not CLK0.

> 
> In BASE mode the incoming clock frequency can be multiplied by any
> integer from 1 to 32, or the clock frequency can be divided by any
> integer from 2 to 16, as well as divided by the non-integer values of
> 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, and 7.5. The output is edge-aligned with
> the rising CLKIN edge whenever that is mathematically possible. (When
> divided by x.5, only every other output edge is aligned with the input
> edge). For integer multiply and divide ratios, the output is
> automatically adjusted to a 50% duty cycle. 
> In BASE mode, the max frequency limit aplies to input and output
> frequencies, but the min frequency limit of 24 MHz applies only to the
> input frequency.
> 
> In Frequency Synthesis mode,the incoming clock frequency can be
> simultaneously multiplied and divided by any integer from 1 through 32.
> A 200 MHz input, for example, can be multiplied by 19 and divided by 20
> to generate a 190 MHz output. Since multiplication and division are
> performed mathematically, no 3.8 GHz internal frequency is generated. In
> FS mode, the max frequency limit aplies to input and output
> frequencyies, but the min frequency limit of 24 MHz applies only to the
> output (!) frequency.  
> 
> Note the difference: 
> In BASE mode it's the input frequency that must be above 24 MHz, 
> in FS mode it's the output frequency.
> 
> Practical examples in BASE mode: 
> 26 MHz : 13 =  2.0 MHz,  
> 250 MHz : 2.5 = 100 MHz,  
> 50 MHz x 5 = 250 MHz
> 
> Practical examples in Frequency Synthesis mode:
> 10 MHz x 31 : 5 =  62 MHz      
> 200 MHz x 27 : 20 = 270 MHz
> 
> Not possible:
> 20 MHz : 5 = 4 MHz 
> ( input frequency is too low for BASE mode, and output frequency is too
> low for FS mode. Use flip-flop dividers instead)
> 
> 7 MHz x 6 : 5 = 8.4 MHz 
> (output frequency is too low, change to  
> 7MHz x 24 : 5 = 33.6 MHz 
> and use two flip-flops to divide by the output by 4.) 
> 
> The flip-flops can then drive the global clock buffer, but do not
> guarantee the tight delay specification offered by the DCM. Note however
> that phase coherence in FS mode obviously can occur only once every D
> input cycles = once every M output cycles, and usually is irrelevant in
> a real application.
> 
> Input Jitter:
> The DCM  is guaranteed to tolerate max 1 ns of cycle to cycle jitter on
> its input. Higher jitter can cause the DCM  to loose lock, which is then
> indicated on the Lock output going High, or the CLKFX_Stopped bit going High.
> 
> Output jitter:
> Use the software tools to calculate the output jitter. There are
> additional software tools available to evaluate the effect of M and D on
> the output jitter. Contact your FAE..
> 
> Phase Shift Operation:
> The DCM  can provide phase-shifted outputs. 
> 
> In BASE mode, it provides the input frequency with four phase angles (
> 0, 90, 180, and 270 degrees), as well a the double frequency and the
> double frequency inverted (180 degr)
> 
> In Phase Shifted (PS) mode, all outputs are shifted by a common amount,
> defined by an 8-bit control word N that specifies the phase shift of
> N/256 times the incoming clock period. The granularity is also limited
> by the delay chain increments, roughly 30 ps. This determines the
> effective resolution for frequencies above 150 MHz. 
> The user can specify any one of 256 values, and the DCM will make the
> closest possible approximation, within 30 ps. 
> The value N is usually set by configuration, but can also be adjusted
> dynamically during operation.
> 
> I hope this long posting is helpful.
> Peter Alfke, Xilinx Applications

Regards Patrik Eriksson

Hi Peter,
CLKIN doesn't need to be free running when the DCM is locked, unless
you're using CLKFX or CLKFX180. Here's a quote from the user guide.
<quote>
Input Clock Changes
Changing the period of the input clock beyond the maximum input period
jitter specification requires a manual reset of the DCM. Failure to
reset the DCM produces an unreliable lock signal and output clock.
While the DCM is in the locking process, no input clock edge can be
missing. Once locked, it is possible to temporarily stop the input
clock with little impact to the de-skew circuit, as long as CLKFX or
CLKFX180 is not used.
</quote>
Complicated things, those DCMs!
Cheers, Syms.

Peter Alfke <peter@xilinx.com> wrote in message news:<4044CEE5.15179D88@xilinx.com>...
> Basic functionality:
> In its simplest use, the DCM  eliminates the clock delay between the
> incoming clock signal and the low-skew global clock distribution. With
> the appropriate feedback to its CLKFB input the DCM  inserts the right
> amount of delay so that CLKIN and CLKO signals occur simultaneously
> (within a very small fraction of a nanosecond). Physically, CLKO is
> delayed by exactly one clock period, and this obviously requires a
> free-running, constant-frequency CLKIN.
> I hope this long posting is helpful.
> Peter Alfke, Xilinx Applications

Hi, Symon.
Literally, you are right. Under some circumstances the CLKIN is allowed to
stop for a very short time. But the ramifications are so strange (the output
keeps going for a while, and then does not start immediately when CLKIN
comes back) that I preferred to ignore this limited capability.
"Free-running" covers 99.9% of the applications.
Peter Alfke


> From: symon_brewer@hotmail.com (Symon)
> Organization: http://groups.google.com
> Newsgroups: comp.arch.fpga
> Date: 5 Mar 2004 09:24:33 -0800
> Subject: Re: CASCADING DCM
> 
> Hi Peter,
> CLKIN doesn't need to be free running when the DCM is locked, unless
> you're using CLKFX or CLKFX180. Here's a quote from the user guide.
> <quote>
> Input Clock Changes
> Changing the period of the input clock beyond the maximum input period
> jitter specification requires a manual reset of the DCM. Failure to
> reset the DCM produces an unreliable lock signal and output clock.
> While the DCM is in the locking process, no input clock edge can be
> missing. Once locked, it is possible to temporarily stop the input
> clock with little impact to the de-skew circuit, as long as CLKFX or
> CLKFX180 is not used.
> </quote>
> Complicated things, those DCMs!
> Cheers, Syms.
> 
> Peter Alfke <peter@xilinx.com> wrote in message
> news:<4044CEE5.15179D88@xilinx.com>...
>> Basic functionality:
>> In its simplest use, the DCM  eliminates the clock delay between the
>> incoming clock signal and the low-skew global clock distribution. With
>> the appropriate feedback to its CLKFB input the DCM  inserts the right
>> amount of delay so that CLKIN and CLKO signals occur simultaneously
>> (within a very small fraction of a nanosecond). Physically, CLKO is
>> delayed by exactly one clock period, and this obviously requires a
>> free-running, constant-frequency CLKIN.
>> I hope this long posting is helpful.
>> Peter Alfke, Xilinx Applications