On Jan 21, 10:14 am, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote:> On 2009-01-21, jleslie48 <j...@jonathanleslie.com> wrote: > > > and ironically the sample chapter supplied on that webpage is exactly > > the chapter that I am interested in: > > >http://academic.csuohio.edu/chu_p/rtl/fpga_vhdl_book/fpga_vhdl_sample... > > I took a brief look at this and happened to notice that the author forgot > to synchronize the rx input signal. So if you follow this example, add > one flip-flop to avoid race conditions and another flip-flop to reduce > the probability of metastability issues to near zero. I have emailed the > author about this so hopefully he'll fix this. (Well, that or I just > missed the synchronization which would be very embarrasing for me :)) > > If you are not aware of why you need to synchronize an input signal you > could read a longer post I wrote at the following URL:http://groups.google.se/group/comp.arch.fpga/browse_thread/thread/6b6... > > Or you could of course look it up in some textbook on digital design. > > /Andreasyes, I remember that thread, I have to admit, I didn't quite follow that part so well. I will be re-visiting this shortcoming of this implementation of the RS232 but for now lets just get our feet wet. Here's my version of a blog on how to get this UART working. Its a complete backup of my workspace on the project in its natural tree form, and there is also a zip file of the project if you want to download it in one fail swoop (3mb) the backup is here: http://jleslie48.com/fpga_uartjl_01/ and the zip file of that is here: http://jleslie48.com/fpga_uartjl_01/zip090120a_fpga_uartjl_01.zip You will also notice a notes sub-directory where these notes and discoveries are being documented here: http://jleslie48.com/fpga_uartjl_01/notes/ I even used microsoft word to try and clean up the notes.txt file a bit. Anyway, here is the project so far, and I'd appreciate some insight as detailed in step 6) below. - Jon Notes.txt: 090120 - ok so I started this project and I admit it, I'm scared and I don't really know what I'm doing. I have the Digilent Virtex-II development system with the ISE 10.1 and Impact 10.1 software packages: http://www.xilinx.com/products/devkits/XUPV2P.htm This project started with the sources and chapter 7 of: FPGA PROTOTYPING BY VHDL EXAMPLES Xilinx SpartanTM-3V ersion Pong P. Chu Cleveland State University the authors website has even a download of the examples: http://academic.csuohio.edu/chu_p/rtl/fpga_vhdl.html and even chapter 7 as a pdf file: http://academic.csuohio.edu/chu_p/rtl/fpga_vhdl_book/fpga_vhdl_sample_chapter.pdf In this backup of my project, all the examples from the book are stored in this tree as \vhdl_examples and all the sources I think I need are stored in \orig because I'm sure I'll be modifying them and so I wanted to store off my originals. as I make milestones, I imagine new directories of backups will emerge, named \buxx_somethingdescriptive as this forray will also be kept online, I will zip it up and store it in the root directory under zipYYMMDDx_somethingdescriptive.zip so anyone wishing to follow in my footsteps or play along can do so. with that said lets begin. 1) I started a new project with ISE 10.1 Project Navigator. 2) after that huba-balloo, I clicked 'add existing source' and added all the source I thought I needed from the examples. I had previously put copies of those sources in the root of the project. I even took a screencap: \notes\screencap01_firstsource.png http://jleslie48.com/fpga_uartjl_01/notes/screencap01_firstsource.png so far so good. 3) I then clicked 'synthesize -XST'. The arrows chasing each other thingy changed after a few seconds to a spinny type thingy and the bottom view section started spewing all kinds of report stuff. All well and good and I ended up with some warnings, which I'd like to discuss a little later. Here's the screen cap: \notes\screencap02_firstsynth.png http://jleslie48.com/fpga_uartjl_01/notes/screencap02_firstsynth.png the error messages are: Analyzing Entity <uart_test> in library <work> (Architecture <arch>). WARNING:Xst:753 - "C:/jon/fpga_uartjl_01/uart_test.vhd" line 29: Unconnected output port 'db_level' of component 'debounce'. Entity <uart_test> analyzed. Unit <uart_test> generated. Analyzing generic Entity <uart> in library <work> (Architecture <str_arch>). DBIT = 8 DVSR = 163 DVSR_BIT = 8 FIFO_W = 2 SB_TICK = 16 WARNING:Xst:753 - "C:/jon/fpga_uartjl_01/uart_core.vhd" line 37: Unconnected output port 'q' of component 'mod_m_counter'. WARNING:Xst:753 - "C:/jon/fpga_uartjl_01/uart_core.vhd" line 46: Unconnected output port 'full' of component 'fifo'. Entity <uart> analyzed. Unit <uart> generated. Now I haven't used a UCF file yet, and I believe that I must, so I'd like to discuss that in a very short time period, but let's continue with what I have done so far. 4) I then hit the 'implement design' arrow thingy. It was very obedient and started spinning as well. whe it was all done it was very happy. No errors or warnings. Here's the screen cap of that result: \notes\screencap03_firstimplement.png http://jleslie48.com/fpga_uartjl_01/notes/screencap03_firstimplement.png 5) checking the pinouts. well somewhere in my travels, someone mentioned looking at the pinout report for useful stuff. so here it is: \notes\screencap04_firstpinoutrpt.png http://jleslie48.com/fpga_uartjl_01/notes/screencap04_firstpinoutrpt.png 6) well now I want to take a break and review a few things, I can see that my pinout report has some useful stuff and some not-so useful stuff. for instance, RX and TX I think have to somehow be associated to the DB9 that is on my board (the root directory has a UCF file RS232.UCF in it, that I believe I should use, and the pinouts of this "hard" uart should be properly level shifted yes?) This example also assumed a spartan 3 evaluation kit which I guess has a digital readout and I think that is what those led<x> things are, so I want to get rid of those. I also have a question about the clock situation. the chapter describes that all the communication is to be synched up with a clock pulse divided by 16 * something or other (see 7.2.2) now this is all well and good, but I imagine my system clock is different (ok, I admit it, I don't even know where it is.) and so those calculations need to be adjusted. So at this point I'm looking for advice and review of my work so far. Can anybody give some insight into the issues I've raised in 6) above?
rank beginner here, need to know where to start to get RS232 comm's working, and ...
Started by ●November 14, 2008
Reply by ●January 21, 20092009-01-21
Reply by ●January 22, 20092009-01-22
>> If you are not aware of why you need to synchronize an input signal you >> could read a longer post I wrote at the following URL:http://groups.google.se/group/comp.arch.fpga/browse_thread/thread/6b6... >> >> Or you could of course look it up in some textbook on digital design. >> >> /Andreas > >yes, I remember that thread, I have to admit, I didn't quite follow >that part so well. I will be re-visiting >this shortcoming of this implementation of the RS232 but for now lets >just get our feet wet.You really really really want to understand that area. -- These are my opinions, not necessarily my employer's. I hate spam.
Reply by ●January 22, 20092009-01-22
On Jan 22, 6:22 am, hal-use...@ip-64-139-1-69.sjc.megapath.net (Hal Murray) wrote:> >> If you are not aware of why you need to synchronize an input signal you > >> could read a longer post I wrote at the following URL:http://groups.google.se/group/comp.arch.fpga/browse_thread/thread/6b6... > > >> Or you could of course look it up in some textbook on digital design. > > >> /Andreas > > >yes, I remember that thread, I have to admit, I didn't quite follow > >that part so well. I will be re-visiting > >this shortcoming of this implementation of the RS232 but for now lets > >just get our feet wet. > > You really really really want to understand that area. > > -- > These are my opinions, not necessarily my employer's. I hate spam.I fully expect to fall into that hole. I think the best way to learn that lesson will be to crawl out of it. meantime, here is the latest of my build: ERROR:ConstraintSystem:59 - Constraint <NET "RS232_DSR_OUT" LOC = "AD10";> ERROR:ConstraintSystem:59 - Constraint <NET "RS232_CTS_OUT" LOC = "AE8";> ERROR:ConstraintSystem:59 - Constraint <NET "RS232_RTS_IN" LOC = "AK8";> ERROR:ConstraintSystem:59 - Constraint <NET "RS232_DSR_OUT" IOSTANDARD = ERROR:ConstraintSystem:59 - Constraint <NET "RS232_CTS_OUT" IOSTANDARD = ERROR:ConstraintSystem:59 - Constraint <NET "RS232_RTS_IN" IOSTANDARD = ERROR:ConstraintSystem:59 - Constraint <NET "RS232_DSR_OUT" DRIVE = 8;> ERROR:ConstraintSystem:59 - Constraint <NET "RS232_CTS_OUT" DRIVE = 8;> ERROR:ConstraintSystem:59 - Constraint <NET "RS232_DSR_OUT" SLEW = SLOW;> ERROR:ConstraintSystem:59 - Constraint <NET "RS232_CTS_OUT" SLEW = SLOW;> \notes\screen05_firstucferrors.png I don't know why it's just not ignoring the unused signals and now I realized that the UCF file uses the # as a comment out character instead of the the "--" grrrrrrr..... yup that's it. \notes\screen06_ucffixed.png \notes\screen07_pinoutrpt.png Ok, this looks like a I successfully completed 'implement design' added clocks.ucf to move clock to AJ15. all implimented still here's clocks.ucf: NET "clk" LOC = "AJ15"; NET "clk" IOSTANDARD = LVCMOS25; NET "clk" TNM_NET = "clk"; TIMESPEC "TS_clk" = PERIOD "clk" 10.00 ns HIGH 50 %; whatever this means. now for the button,reset, and leds: btn_db_unit: entity work.debounce(fsmd_arch) port map(clk=>clk, reset=>reset, sw=>btn(0), db_level=>open, db_tick=>btn_tick); -- incremented data loop back rec_data1 <= std_logic_vector(unsigned(rec_data)+1); -- led display led <= rec_data; an <= "1110"; sseg <= '1' & (not tx_full) & "11" & (not rx_empty) & "111"; these are all S3 Board specific yes? btn(0) is one of the 4 buttons of the S3 board and I have to find mutatis mutandis on my Digilent board? led(0-7) an(0-3) and sseg(0-7) are what exactly? for functionality I think I only need btn(0) yes? then comes the clk, where is the speed and the divisor value fit in? - I'm guessing its somewhere in those oodles of pdf's that came with te board, I remember ug069.pdf being useful... and for this project reset is just a placeholder yes?
