CycIII Intefacing these new serial ADC's

Hi,

I'm on a design that requires 2 fast ADC (14bit 100Ms/s)
and an FPGA.

So far all all plans were based on parallel data to the FPGA, but
I must confess these new serial ADC's are tempting
specially the ADS6244 that fits perfectly with my intentions.
(2ch 14bit 125Ms/s in a single package and a few lvds lines only 
interfacing the FPGA)

But I fear the interfacing to an ALtera CycloneIII.
The required will be; serial data at 700Mb/s
and serial clock at 350MHz (DDR)

I would certainly be confident with one of the
high end FPGA's but I can't use anything except
the low cost ones ;-)

I have no problem in doing a proper layout
with all cares about line length and impedances
but...
Is that what it takes and the rest is easy enough ?

I do fear input and inside the FPGA...
too marginal for a CycloneIII to do ?....

is it too hard/difficult ?
does a shift register and word transfer
register design described in VHDL, suffice for the input
deserializer or something fancier is needed ?


Or in the end...
Will I be better off with parallel bus ADC's ?


I'm having trouble to decide myself...

I'll be very happy to hear some comments please.
Thanks.


Luis C.