cpld 9572 xilinx

                   Currently i am doing my final year  project on
xilinx cpld 9572

    How do we can access registers in this cpld using vhdl .......

On Feb 16, 9:49=A0pm, melvin <melvinv...@gmail.com> wrote:
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Currently i am doing my final year=
 =A0project on
> xilinx cpld 9572
>
> =A0 =A0 How do we can access registers in this cpld using vhdl .......

Search for some simple examples (which may not be 9572 specific), and
re-target the device to 9572 (or other family members).

Then, look at the tool-flow fitter report files, to see what resource
was
used, and you will learn how the code maps to macrocells.

-jg

On Feb 16, 3:49=A0am, melvin <melvinv...@gmail.com> wrote:
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0Currently i am doing my final year=
 =A0project on
> xilinx cpld 9572
>
> =A0 =A0 How do we can access registers in this cpld using vhdl .......

A XC9572 has 72 macro cells (MC), and each MC has a flip-flop.  Flip-
flops are used in counters, registers, and state machines.  This type
of info should be in your text books!
After you -synthesize- your design, you can use ISE's RTL viewer to
see a logic diagram of the results.  If you need examples, ISE has
them:
Edit/language templates/VHDL/Synthesis Constructs/Coding Examples
But please, use "rising_edge(clock)" instead of "<clock>'event and
<clock>=3D'1'".  It's "better", and it's less typing ;)
HTH
-Dave Pollum