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Can Xilinx IST automatically detect non-compatible library?

Started by Weng Tianxiang February 25, 2009
Hi,
When I was generating my code, I didn't know what exact Xilinx chip
may be used so that I selected Virtex V chip as my target one time.
During the development, I might have tried to generate libraries with
Virtex II chips because I have many Virtex II libraries ready to use.
It led to the situation that I really don't know which library belongs
to which chip. For simulations, it doesn't matter. But now I am trying
to implement my design on Virtex II chip, the problem comes clear: if
all libraries used in my simulation are for Virtex II? I can't answer
the question.

So I would like to ask if Xilinx IST can automatically detect an error
when a Virtex V chip library is used for a Virtex II chip project. I
think it is. But to reduce risks of errors, I would like to ask
experienced persons for a positive answer without any guess.

Thank you.

Weng

On Feb 25, 9:05 am, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi, > When I was generating my code, I didn't know what exact Xilinx chip > may be used so that I selected Virtex V chip as my target one time. > During the development, I might have tried to generate libraries with > Virtex II chips because I have many Virtex II libraries ready to use. > It led to the situation that I really don't know which library belongs > to which chip. For simulations, it doesn't matter. But now I am trying > to implement my design on Virtex II chip, the problem comes clear: if > all libraries used in my simulation are for Virtex II? I can't answer > the question. > > So I would like to ask if Xilinx IST can automatically detect an error > when a Virtex V chip library is used for a Virtex II chip project. I > think it is. But to reduce risks of errors, I would like to ask > experienced persons for a positive answer without any guess. > > Thank you. > > Weng
Simulation libraries and Synthesis libraries are different. XST does check synthesis libraries. PAR will fail if the wrong libraries are linked. AL
On Feb 25, 9:30=A0am, LittleAlex <alex.lo...@email.com> wrote:
> On Feb 25, 9:05 am, Weng Tianxiang <wtx...@gmail.com> wrote: > > > > > > > Hi, > > When I was generating my code, I didn't know what exact Xilinx chip > > may be used so that I selected Virtex V chip as my target one time. > > During the development, I might have tried to generate libraries with > > Virtex II chips because I have many Virtex II libraries ready to use. > > It led to the situation that I really don't know which library belongs > > to which chip. For simulations, it doesn't matter. But now I am trying > > to implement my design on Virtex II chip, the problem comes clear: if > > all libraries used in my simulation are for Virtex II? I can't answer > > the question. > > > So I would like to ask if Xilinx IST can automatically detect an error > > when a Virtex V chip library is used for a Virtex II chip project. I > > think it is. But to reduce risks of errors, I would like to ask > > experienced persons for a positive answer without any guess. > > > Thank you. > > > Weng > > Simulation libraries and Synthesis libraries are different. > > XST does check synthesis libraries. =A0PAR will fail if the wrong > libraries are linked. > > AL- Hide quoted text - > > - Show quoted text -
Hi Al, Can I have a text editor software to find which type of chips a library belongs to? So that I don't have to wait for PAR error to happen. I remember *.edn files are libraried for synthesis. But I couldn't find any keyword about the chip in a *.edn file. Weng