Xilinx user constraints with respect to output clock from the design

Hi,

Sdram signals are going out of my design to a SDR SDRAM. This SDR SDRAM
requires a setup time of 3.8 ns. The clock to SDRAM is provided by the
design which is generated from the DCM with the source clock at 40 Mhz. I
tried to put output constraints on other SDRAM control signals with respect
to the clock generated in the design(to meet the setup time of SDRAM). But
it is showing error as we should not put a constraint with respect to a
output signal. If I put the constraints with respect to the input clock to
the design, the working of the sdram is depending on the placement of the
design in FPGA. Like, If I add chipscope signals it is working and if i
dont add chipscope signals it is not working. In both cases the signals are
going out of the FPGA as required. This I think is because of not meeting
the setup time required. So, how can I ensure that the other SDRAM control
signals are shifted by 3.8ns with respect to the SDRAM clock.

Just make sure you specify your clock period in the ucf file and that it
passes the static timing report. You shouldnt need to add any other timing
constraints in the ucf. I did a sdram design a while back running at 100MHz
which worked just fine using the above procedure.

Cheers

Jon

Hi,
In that case if the output clock to sdram which comes from design is, say
suppose, 10ns after input clock and the address to sdram which is of 13 bit
width is such that first 5 lines (4 down to 0) arrive before  the clock to
sdram and the remaninig lines arrive after the clock, then the setup time
is met for only the first 5 lines of address bus and if give the address as
16'h124 it will write to address location 4 (first five bits of 16'h124).
Is my argument correct? If not, please explain.

Thanks,
gangi

You need to ensure that your output signals have the required setup time
relative to your output clock. What I usually do is to clock these signals
using the clk90 output of the DCM. That way you should easily meet the
setup time.

Jon

Thank you Jon.

On Apr 8, 9:33=A0am, "maxascent" <maxasc...@yahoo.co.uk> wrote:
> You need to ensure that your output signals have the required setup time
> relative to your output clock. What I usually do is to clock these signal=
s
> using the clk90 output of the DCM. That way you should easily meet the
> setup time.
>
> Jon

To get even tighter timing between outputs, you should ensure that
all output registers are pushed into the IOB's.  This gives very
low skew between outputs switching on the same clock.  Then using the
quadrature clock gives you data centered around the clock edge
for DDR designs.