Hi everyone, I'm just about to start an implementation of an open spacewire IP core (still trying to understand under which license, GPL, LGPL, CeCILL...) and I was wondering whether is a good idea to have a wishbone interface implemented. I am pretty new to SoC bus and even though google is "one of my best friends" I still didn't get the feeling how popular it is and how spread it is at the moment or will be in the future. If anyone has any opinion I would be glad to listen to it. Thanks a lot, Al -- Alessandro Basili CERN, PH/UGC Hardware Designer
wishbone
Started by ●March 19, 2010
Reply by ●March 19, 20102010-03-19
On Fri, 19 Mar 2010 16:29:54 +0100 Alessandro Basili <alessandro.basili@cern.ch> wrote:> Hi everyone, > I'm just about to start an implementation of an open spacewire IP > core (still trying to understand under which license, GPL, LGPL, > CeCILL...) and I was wondering whether is a good idea to have a > wishbone interface implemented. > I am pretty new to SoC bus and even though google is "one of my best > friends" I still didn't get the feeling how popular it is and how > spread it is at the moment or will be in the future. > If anyone has any opinion I would be glad to listen to it. > Thanks a lot, > > Al >I use it a lot on my projects, though I rarely bring in any 3rd party IP. The thing about a WISHBONE bus is that it's really just a consistent way of naming the minimal set of signals you'd need to have a SoC bus. Data, address, chip select, read/write, return data and a handshake. As compared to other SoC buses I've looked at, WISHBONE takes far less coding effort to deliver somewhat less performance. It's a simple enough thing that you can make practically any kind of slave, or any kind of master, talk to it. The lack of pipelining can kill your throughput if you're really having to push a lot of data, but for most applications it's plenty sufficient. -- Rob Gaddi, Highland Technology Email address is currently out of order
Reply by ●March 19, 20102010-03-19
On Mar 19, 8:29=A0am, Alessandro Basili <alessandro.bas...@cern.ch> wrote:> Hi everyone, > I'm just about to start an implementation of an open spacewire IP core > (still trying to understand under which license, GPL, LGPL, CeCILL...) > and I was wondering whether is a good idea to have a wishbone interface > implemented. > I am pretty new to SoC bus and even though google is "one of my best > friends" I still didn't get the feeling how popular it is and how spread > it is at the moment or will be in the future. > If anyone has any opinion I would be glad to listen to it. > Thanks a lot, > > Al > > -- > Alessandro Basili > CERN, PH/UGC > Hardware DesignerI have worked with 3 "externally defined" on-chip buses: 1) Avalon (Altera) 2) OPB (sp?) (Xilinx) 3) Wishbone (GPL/Lattice) Semi-random opinions: Expanding on Rob's comment, using a bus that "someone else" defines means that there's one less definition that *you* have to do; this is a good thing. The NIOS and EDK buses are mostly useful in their manufacturer's tool- chain, and their devices. The translation from Avalon to Wishbone is trivial though. I had to sign an 'NDA' with IBM to get the documentation for the EDK bus. This didn't make a lot of sense to me. The Wishbone is popular enough that IP vendors will code to it without a lot of resistance. This isn't always true with proprietary buses. There you go; a bunch of reasons to use it, and none (so far) to NOT use it. RK
Reply by ●March 19, 20102010-03-19
"Alessandro Basili" <alessandro.basili@cern.ch> wrote in message news:ho059b$hpl$1@speranza.aioe.org...> Hi everyone, > I'm just about to start an implementation of an open spacewire IP core (still > trying to understand under which license, GPL, LGPL, CeCILL...) and I was > wondering whether is a good idea to have a wishbone interface implemented.Depending on what you want to do with the core but I would suggest you also have a look at the Amba bus since (thanks to Gaisler research?) this bus seems to be gaining popularity amonst the space/mil-aero users. Hans www.ht-lab.com> I am pretty new to SoC bus and even though google is "one of my best friends" > I still didn't get the feeling how popular it is and how spread it is at the > moment or will be in the future. > If anyone has any opinion I would be glad to listen to it. > Thanks a lot, > > Al > > -- > Alessandro Basili > CERN, PH/UGC > Hardware Designer
Reply by ●March 19, 20102010-03-19
On 3/19/2010 5:56 PM, HT-Lab wrote:> > Depending on what you want to do with the core but I would suggest you also have > a look at the Amba bus since (thanks to Gaisler research?) this bus seems to be > gaining popularity amonst the space/mil-aero users. >Indeed I was trying to understand the main differences just because I know that there are IP cores available which are interfaced with AMBA, but the main idea behind is to have a copyleft license on the core, mainly to share it in the academic community, especially for those science projects which are space related. Al -- Alessandro Basili CERN, PH/UGC Hardware Designer
Reply by ●March 20, 20102010-03-20
>Hi everyone, >I'm just about to start an implementation of an open spacewire IP core >(still trying to understand under which license, GPL, LGPL, CeCILL...) >and I was wondering whether is a good idea to have a wishbone interface >implemented. >I am pretty new to SoC bus and even though google is "one of my best >friends" I still didn't get the feeling how popular it is and how spread >it is at the moment or will be in the future. >If anyone has any opinion I would be glad to listen to it. >Thanks a lot, > >Al > >-- >Alessandro Basili >CERN, PH/UGC >Hardware Designer >Yes and no, First create your core logic as a "headless" design with no bus interface. Make a testbench that directly drives and tests the ports of this core design. Then create a module with a wishbone interface and connections for all the ports of your core that do not connect to a higher level. Your design will consist of a wrapper containing these two modules. Copy your test suite and rewrite it to use the wishbone bus where needed. DO NOT create a wishbone interface and then place your core logic below it in the hierarchy. If you do and then later want to support a different bus then you are screwed. If you keep the wishbone in one module then it is alot easier to take that module and convert it into something like a AHB bus. You want to be able to add new buses without touching the core. John --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●March 21, 20102010-03-21
> Yes and no, > > First create your core logic as a "headless" design with no bus interface. > Make a testbench that directly drives and tests the ports of this core > design. > > Then create a module with a wishbone interface and connections for all the > ports of your core that do not connect to a higher level. Your design will > consist of a wrapper containing these two modules. Copy your test suite and > rewrite it to use the wishbone bus where needed. > > DO NOT create a wishbone interface and then place your core logic below it > in the hierarchy. If you do and then later want to support a different bus > then you are screwed. If you keep the wishbone in one module then it is > alot easier to take that module and convert it into something like a AHB > bus. > You want to be able to add new buses without touching the core.Hi John, I completely got your point and I'm really happy you pointed that out, because most probably I would have made a big mistake! It makes perfectly sense to me and it's surely the way I will go. Thanks again, Al p.s.: funny how very simple ideas sometimes are not so evident to all of us. -- Alessandro Basili CERN, PH/UGC Hardware Designer
