verilog task and vhdl

On 6/5/2011 10:53 AM, Mike Treseler wrote:
> Your choices are:
> 1. Buy a license and write vhdl procedures for the verilog uut.
> 2. Learn verilog and write a verilog testbench.
> 3. Write your own phy model in vhdl.
> 

I believe there's a forth. Since the model "has already been tested
deeply" I would create the vhdl model out of the back annotation that it
certainly has (I used to do that with Designer for Actel devices).

Once you have your PHY_ba.vhd you simply include it in your simulation
and you instantiate it in your testbench as you would do normally with a
component written in vhdl.

If your PHY model never went through a post-layout simulation I hardly
doubt it was "tested deeply" and I would seriously reconsider the first
three options listed by Mike.

Al