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About eseke

Erol Seke (@eseke)

Interest areas : Communication, signal processing, image processing, FPGA, Programming Work : Teach at Eskisehir Osmangazi University, Department of Electrical-Electronics Engineering and Computer Engineering Web Page : eseke.ogu.edu.tr

Re: Simple logic

Reply posted 7 years ago (12/27/2016)
It looks like it is just a FF set by rising edge of S1 and reset by rising edge of S2. A fully synchronous design should look like;process(clk) is begin if(rising_edge(clk))...

Re: Mealy or Moore? none and not even state machine

Reply posted 8 years ago (09/30/2016)
I would suggest a shift/rotate register initialized to 1000...0 (a bit per state) and check only a single bit per state.Other state machines and counter approaches...

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