The Designer's Guide to VHDL
Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs.
VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools.
This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals.
* Details how the new standard allows for increased portability across tools.
* Covers related standards, including the Numeric Synthesis Package and the Synthesis Operability Package, demonstrating how they can be used for digital systems design.
* Presents four extensive case studies to demonstrate and combine features of the language taught across multiple chapters.
* Requires only a minimal background in programming, making it an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD.
Why Read This Book
You should read this book if you want a single, authoritative reference that explains VHDL's semantics, idioms and synthesis implications in depth. It teaches you practical, industry-proven modelling and testbench techniques so you can write robust, synthesizable HDL for real FPGA/ASIC projects.
Who Will Benefit
FPGA/ASIC designers and verification engineers with some digital-design background who need a thorough, practical reference to write, synthesize, and verify VHDL models.
Level: Intermediate — Prerequisites: Basic digital logic (combinational/sequential circuits) and familiarity with programming concepts (variables, control flow); no prior VHDL required but helpful to have some HDL exposure.
Key Takeaways
- Describe digital hardware using VHDL's concurrent, structural, and sequential constructs effectively.
- Write modular, reusable VHDL using packages, generics, configurations and subprograms.
- Build robust testbenches and apply simulation techniques to validate and debug designs.
- Apply synthesis-friendly coding styles and understand what language features synthesize to hardware.
- Analyze timing, signal resolution and concurrency to avoid common modeling pitfalls.
- Map VHDL designs into FPGA/ASIC implementation flows and reason about tool interactions.
Topics Covered
- Introduction: VHDL in the design flow
- Lexical elements, design units and basic syntax
- Objects, types, signals and variables
- Concurrent statements and structural modelling
- Sequential statements, processes and control flow
- Subprograms, procedures, functions and packages
- User-defined types, records, arrays and resolution functions
- Configuration, binding and hierarchical design
- Attributes, file I/O and advanced language features
- Testbenches, simulation semantics and debugging
- Synthesis issues, coding styles and best practices
- Timing models, delays and physical considerations
- Verification strategies and design examples
- Appendices: language summary and reference
Languages, Platforms & Tools
How It Compares
More authoritative and language-centric than Douglas L. Perry's 'VHDL: Programming by Example' (which is more tutorial-oriented), and more complete as a reference than Bhasker's 'A VHDL Primer'.
