Architecture of FPGAs and CPLDs: A Tutorial

Stephen Brown, Jonathan Rose

Still RelevantIntermediate

This paper provides a tutorial survey of architectures of commercially available high-capacity ﬁeld-programmable devices (FPDs). We ﬁrst deﬁne the relevant terminology in the ﬁeld and then describe the recent evolution of FPDs. The three main categories of FPDs are delineated: Simple PLDs (SPLDs), Complex PLDs (CPLDs) and Field-Programmable Gate Arrays (FPGAs). We then give details of the architectures of all of the most important commercially available chips, and give examples of applications of each type of device.

Summary

This tutorial survey presents a clear, vendor-focused overview of SPLD, CPLD, and FPGA architectures and how they evolved. Readers will learn the structural building blocks of commercial devices and practical implications for mapping designs and applications such as DSP.

Key Takeaways

Differentiate the structural and functional differences between SPLDs, CPLDs, and FPGAs to choose the right device class for a design.
Identify key vendor architecture decisions (e.g., LUTs, CLBs, routing fabrics) in Xilinx and Intel/Altera devices and how they affect synthesis and performance.
Analyze on-chip resources — BRAM, DSP slices, and embedded logic — to optimize placement of DSP and memory-heavy functions.
Apply architectural knowledge to predict routing congestion, timing behavior, and implementation trade-offs across device families.

Who Should Read This

Intermediate FPGA and digital logic designers, FPGA architects, and system engineers who need to understand device architectures, vendor trade-offs, and how to map designs across SPLD/CPLD/FPGA families.

Still RelevantIntermediate