Now - not so new cheaper FPGAs

Started by rickman in comp.arch.fpga4 months ago 5 replies

I have used the Lattice XP3 FPGAs in a design I've made a lot of money from. The parts have gone EOL but Arrow bought some 70,000+ and is...

I have used the Lattice XP3 FPGAs in a design I've made a lot of money from. The parts have gone EOL but Arrow bought some 70,000+ and is still trying to get rid of them. Seems they over estimated the market. I had to pay a higher price to them in 2016 than I paid when they were in production (~$10) but now they are going for around $5-$6 depending on quantity and they still have 65,...


New(ish) FPGA Company

Started by Anonymous in comp.arch.fpga4 months ago 17 replies

I hadn't heard of this company before. They seem to be making a number of FPGA devices. Unfortunately all the docs are in Chinese. Anyone know...

I hadn't heard of this company before. They seem to be making a number of FPGA devices. Unfortunately all the docs are in Chinese. Anyone know much about them? http://www.anlogic.com/ Google can translate the web pages, but not the data sheets. Rick C.


Need Information about Implementing of Modbus protocol in fpga ( mostly spartan 6)

Started by Swapnil Patil in comp.arch.fpga4 months ago 3 replies

Hello folks, I wanted to implement Modbus protocol on fpga. I don't know how to start? I read various documents on internet but...

Hello folks, I wanted to implement Modbus protocol on fpga. I don't know how to start? I read various documents on internet but didn't got any clear idea. basically my aim is to make package of this protocol. I am using Vhdl as language. so i want process or say steps should i follow to make this protocol working.If anybody has worked on this previously can share docum


Simple system to manage register access in hierarchical Wishbone-connected FPGA designs.

Started by Anonymous in comp.arch.fpga4 months ago

Hi, I needed to provide convenient access to registers in an FPGA design internally interconnected with Wishbone/IPbus bus. There is a...

Hi, I needed to provide convenient access to registers in an FPGA design internally interconnected with Wishbone/IPbus bus. There is a wonderful tool - wbgen2 in the OHWR directory, but it doesn't support nested slaves neither vectors of registers. Therefore, I've decided to prepare a similar tool, based on wbgen2 concept, but written in Python. The first version is already availab


who knows how to make 480P HDMI output in VHDL code ?

Started by Anonymous in comp.arch.fpga4 months ago

code used from hamsterworks.co.nz/mediawiki/index.php/Minimal_HDMI

code used from hamsterworks.co.nz/mediawiki/index.php/Minimal_HDMI


Strange thing, my FPGA HDMI output cannot work with cheap chinese HDMI Extender

Started by Anonymous in comp.arch.fpga4 months ago 8 replies

I bought HDMI extender over optical fiber for $125, from Alibaba. HDMI Extender works well when Source is my laptop, but when source is my FPGA...

I bought HDMI extender over optical fiber for $125, from Alibaba. HDMI Extender works well when Source is my laptop, but when source is my FPGA board,there is a problem. I enabled TMDS, HPD, DDC, 5+, ground as in Hamsterwork's project , it doesnot works,I dont know why? Who had the same situation ? What to do ? Alibaba seller know nothing about this, but they always tell me they manufactu...


FPGA Market Entry Barriers

Started by Anonymous in comp.arch.fpga4 months ago 57 replies

I was wondering what the barriers are to new companies marketing FPGAs. Some of the technological barriers are obvious. Designing a novel device...

I was wondering what the barriers are to new companies marketing FPGAs. Some of the technological barriers are obvious. Designing a novel device is not so easy as the terrain is widely explored, so I expect any new player would need to find a niche application of an unexplored technological feature. Silicon Blue exploited a low power technology optimized for low cost device


What to do with an improved algorithm?

Started by Mike Field in comp.arch.fpga5 months ago 18 replies

Hi, I think I've got a really good way to improve a commonly used & well establ= ished algorithm that is often used in FPGAs, and it all...

Hi, I think I've got a really good way to improve a commonly used & well establ= ished algorithm that is often used in FPGAs, and it all checks out. The imp= lementation completes the same tasks in 2/3rds the cycles and using 2/3rds = the resources of an standard Xilinx IP block, with comparable timing). I've verified that the output is correct over the entire range of 32-bit in= put val...


Need magic incantation to prevent synthesizer misoptimisation

Started by Aleksandar Kuktin in comp.arch.fpga5 months ago 2 replies

Hi all! I'm having a problem with the synthesis and P&R tools introducing a unnecessary gate in a critical path. Consider the following...

Hi all! I'm having a problem with the synthesis and P&R tools introducing a unnecessary gate in a critical path. Consider the following verilog: reg [31:0] mem_dataintomem = 32'd0; always @(posedge CLK) begin if (mcu_active && (w_we_recv || w_tlb_recv)) mem_dataintomem


Schematic FPGA Design on twitch

Started by Anonymous in comp.arch.fpga6 months ago 2 replies

tomorrow from 20:15 cet until open end live on my channel https://www.twitch.tv/fpga_guru schematic design on fpga. check it out

tomorrow from 20:15 cet until open end live on my channel https://www.twitch.tv/fpga_guru schematic design on fpga. check it out


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