My invention: Coding wave-pipelined circuits with buffering function in HDL

Started by Weng Tianxiang in comp.arch.fpga4 months ago 42 replies

Hi, A wive-pipelined circuit has the same logic as its pipeline counterpart exc= ept that the wive-pipelined circuit has only one stage, a...

Hi, A wive-pipelined circuit has the same logic as its pipeline counterpart exc= ept that the wive-pipelined circuit has only one stage, a critical path fro= m the input register passing through a piece of computational logic to the = output register, and no intermediate registers. My invention kernel idea is: A designer provides the least information and = logic code about the critical ...


Qs on HDL library code and pipelining

Started by Julio Di Egidio in comp.arch.fpga5 months ago 4 replies

Hello everybody, and Happy New Year 2018! I am new to digital design, here are some basic questions: In particular for algorithm...

Hello everybody, and Happy New Year 2018! I am new to digital design, here are some basic questions: In particular for algorithm acceleration (e.g. arithmetic, cryptography, etc.), does it make sense to think both FPGA and ASIC when writing HDL library code? And, about pipelining combinational logic, what maximum gate-delay granularity would be good (for fmax) on FPGAs? I am guessing...


TinyFPGA Boards

Started by rickman in comp.arch.fpga5 months ago 3 replies

http://tinyfpga.com/ The web site does not work 100% as there are some broken links, but all the pages are there. They currently offer three...

http://tinyfpga.com/ The web site does not work 100% as there are some broken links, but all the pages are there. They currently offer three boards, A1/A2 provide two sizes of the Lattice XO2, the 256 and 1200. These two boards are basically just break out boards with nothing else other than decoupling caps and a ferrite bead. The B2 board uses the ICE40LP8K and comes with an SPI fla...


FPGA one-shot

Started by John Larkin in comp.arch.fpga5 months ago 33 replies

I have an async signal, call it TRIG, inside a Zynq 7020. At the rising edge of TRIG, I want to make an async one-shot. It will leave the...

I have an async signal, call it TRIG, inside a Zynq 7020. At the rising edge of TRIG, I want to make an async one-shot. It will leave the chip as RX and reset some outboard ecl logic. Anything from, say, 2 ns to 10 ns width would work. The board is built, and we can't easily add more connections to the FPGA or hack in glue logic. Well, it would be ugly. Here are some ideas: https:...


graphics for FPGA design

Started by john in comp.arch.fpga6 months ago 2 replies

does anyone have a set of symbols that can help with fpga documentation? (Something for dia perhaps or coreldraw maybe) preferably not...

does anyone have a set of symbols that can help with fpga documentation? (Something for dia perhaps or coreldraw maybe) preferably not visio Or does everyone do this manually all the time? Clearly it's not that complex but what do you all use? -- john ========================= http://johntech.co.uk =========================


additional fpga forums

Started by Edward Moore in comp.arch.fpga6 months ago 4 replies

suggestions for alternative fpga-related forums ?

suggestions for alternative fpga-related forums ?


Test Driven Design?

Started by Tim Wescott in comp.arch.fpga6 months ago 47 replies

Anyone doing any test driven design for FPGA work? I've gone over to doing it almost universally for C++ development, because It Just Works...

Anyone doing any test driven design for FPGA work? I've gone over to doing it almost universally for C++ development, because It Just Works -- you lengthen the time to integration a bit, but vastly shorten the actual integration time. I did a web search and didn't find it mentioned -- the traditional "make a test bench" is part way there, but as presented in my textbook* doesn't impo...


Using LUTs to create a phase delayed clock - is it reproducible?

Started by Aleksandar Kuktin in comp.arch.fpga7 months ago 4 replies

Hi all, I'm making a system on iCE40 and I've ran out of PLLs. The design incorporates two DDR2 controllers that need to perform several...

Hi all, I'm making a system on iCE40 and I've ran out of PLLs. The design incorporates two DDR2 controllers that need to perform several operations delayed with respect to the system clock. I'm gonna use a phase delayed clock for that. So my approach is to take the clock signal and pipe it through several LUTs, thus delaying it. But - how comparable are LUT delays between differen...


Digital-to-Analog Converter LTC 2624, Spartan-3A

Started by m m in comp.arch.fpga7 months ago 9 replies

I would like to know if anyone here has already done a VHDL code to communicate/give commands to the LTC2624 Digital to Analog Converter that...

I would like to know if anyone here has already done a VHDL code to communicate/give commands to the LTC2624 Digital to Analog Converter that has the Spartan-3A starterkit board. I am not asking for the code specifically, but I would like your feedback regarding to this problem: I've a code, which in simulation seems to be all ok, all the timings are met according to the timing specifi...


Beginer's FPGA with SERDES

Started by rickman in comp.arch.fpga7 months ago 10 replies

Some hams want to work with FPGAs to generate high speed PN sequences in the GHz range. LFSR designs are about as simple as you can get in an...

Some hams want to work with FPGAs to generate high speed PN sequences in the GHz range. LFSR designs are about as simple as you can get in an FPGA. The only trick is getting the resulting signal out of the FPGA. Rather than outputting a parallel word at some 100's of MHz into a shift register clocked in the GHz range, it seems easier to use a SERDES to shift it out directly from the F...


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