ADCs in FPGAs

Started by Rick C in comp.arch.fpga6 months ago 7 replies

I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm...

I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it. Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I'm having trouble relating this to the typ


iCE40 Ultra Family Data Sheet

Started by Rick C in comp.arch.fpga6 months ago 7 replies

Looking at section 4.5 the power up supply sequence is clearly stated to start with Vcc/Vccpll, then to bring up SPI_VCCIO1 followed by VPP_2V5...

Looking at section 4.5 the power up supply sequence is clearly stated to start with Vcc/Vccpll, then to bring up SPI_VCCIO1 followed by VPP_2V5 with the remaining supplies to be brought up anytime after Vcc/Vccpll. In each case the prior supplies must reach 0.5V before the next supply should be raised. Then in section 4.6 External Reset, when SPI_V CCIO1 and V PP_2V5 are conne


Potential New Design

Started by Rick C in comp.arch.fpga6 months ago 11 replies

I might be working on a smallish design shortly and I'm picking an FPGA. I= don't have much in the way of requirments yet, but I'd like to have...

I might be working on a smallish design shortly and I'm picking an FPGA. I= don't have much in the way of requirments yet, but I'd like to have at lea= st 2000 LUTs, 39 I/Os or more, but most importantly a board layout friendly= package. That means no BGAs and no CSPs. The board features are just too= small with those. =20 This design is offloading some functionality from an MCU that ...


Is FPGA code called firmware?

Started by Marko in comp.arch.fpga7 months ago 81 replies

Traditionally, firmware was defined as software that resided in ROM. So, my question is, what do you call FPGA code? Is "firmware" appropriate?

Traditionally, firmware was defined as software that resided in ROM. So, my question is, what do you call FPGA code? Is "firmware" appropriate?


Elastic buffer implementation

Started by promach in comp.arch.fpga7 months ago

For this article : Implementing Latency-Insensitive Dataflow Blocks at http://arcade.cs.columbia.edu/lid-memocode15.pdf#page=2 1) How is "Hold"...

For this article : Implementing Latency-Insensitive Dataflow Blocks at http://arcade.cs.columbia.edu/lid-memocode15.pdf#page=2 1) How is "Hold" action different from "Buffer" action ? 2) Why is the '1' pin of the second multiplexer inside the input buffer block fed a symbol of ⊥ ?


Some preliminary help for an FPGA selection

Started by Dimiter_Popoff in comp.arch.fpga7 months ago 4 replies

It will be the first FPGA for me. What I want to do is not complex, I have done similar controllers (more complex really)numerous times using...

It will be the first FPGA for me. What I want to do is not complex, I have done similar controllers (more complex really)numerous times using logic parts, PLD, CPLD-s etc. I need to put together a display controller, to just do framebuffer memory -> display interface. Framebuffer memory will be some sort of DDRAM (DDR-which depending on the FPGA type), I'll be happy with a 1920x1080 framebuf


VLSI SUBSCRIBE

Started by Chip training design in comp.arch.fpga7 months ago

Hi All, ...

Hi All, https://www.youtube.com/watch?v=lT1dj_gmHuM&list=PLesx0GVGgym1bHV1gPIl89wnY0KFflLHj&index=1 https://www.youtube.com/watch?v=YSyz971kuU0&list=PLesx0GVGgym1bHV1gPIl89wnY0KFflLHj&index=10 https://www.youtube.com/watch?v=am6jPpJazx4&list=PLesx0GVGgym1bHV1gPIl89wnY0KFflLHj&index=11 https://www.youtube.com/watch?v=4leMX8s3A0E&list=PLesx0GVGgym1bHV1gPIl89wnY0KFflLHj&index=5 http...


Entity-bound SDC file in Quartus Lite Edition?

Started by Anonymous in comp.arch.fpga7 months ago 1 reply

Hi, I need to port my design from Xilinx FPGA based board to a Altera/Intel FPGA based one. The design must be available for students, who need...

Hi, I need to port my design from Xilinx FPGA based board to a Altera/Intel FPGA based one. The design must be available for students, who need to use the Quartus Lite Edition. One of essential things in the design is the usage of "scoped timing constraints" (obtained in Vivado with SCOPED_TO_REF attribute). I have found that a similar option is available in Quartus as "entity-bound SDC file...


Open source Verilog BCH encoder/decoder

Started by Russell Dill in comp.arch.fpga8 months ago 10 replies

As part of my research, I needed a BCH encoder/decoder engine. Sadly, such = a thing has no existed under a permissive license. Even more...

As part of my research, I needed a BCH encoder/decoder engine. Sadly, such = a thing has no existed under a permissive license. Even more depressing is = that many students seem to submit Verilog or VHDL engines as a project (or = even research), but never release anything that is usable. Anyway, I'm releasing a BSD licensed Verilog BCH encoder/decoder. It offers= : * Parallel input/outp...


Need help finding Synario Futurenet 6.10

Started by Tim Regeant in comp.arch.fpga8 months ago 2 replies

Anyone know where I can find this vintage software? I am looking for the verion 6.10 free with dongle not required. I think Synario was the...

Anyone know where I can find this vintage software? I am looking for the verion 6.10 free with dongle not required. I think Synario was the one to release the free version. Used to be at the ftp site ftp://ftp.synario.com but can't reach it now. Thanks for any help you can offer.


Ask a Question to the FPGARelated community

To significantly increase your chances of receiving answers, please make sure to:

  1. Use a meaningful title
  2. Express your question clearly and well
  3. Do not use this forum to promote your product, service or business
  4. Write in clear, grammatical, correctly-spelled language
  5. Do not post content that violates a copyright