Lattice or Microsemi?

Started by Kevin Bowling in comp.arch.fpga4 months ago 1 reply

What are thoughts on these two vendors goods? I like that they have cheap(er) PCIe options. My intended use case is to learn about HW and...

What are thoughts on these two vendors goods? I like that they have cheap(er) PCIe options. My intended use case is to learn about HW and HDL development with an existing strong OS development background so I want to write device drivers to interface etc. Right now I'm leaning toward Lattice but I like that Microsemi is embracing RISC-V.


Most power efficient FPGA?

Started by Peter S in comp.arch.fpga5 months ago 2 replies

Hi, I have been away from in-depth FPGA development for maybe a decade! I am looking to design an embedded camera product where power use is key....

Hi, I have been away from in-depth FPGA development for maybe a decade! I am looking to design an embedded camera product where power use is key. I'd like to use an FPGA for some video manipulation not much. I used to only use Altera FPGAs, so I know their architecture well enough. It looks like the Cyclone 10 LP is the lowest-power device they have, and their LE structure looks the same as when...


Is Zynq7000 leaky?

Started by Piotr Wyderski in comp.arch.fpga5 months ago 10 replies

Does the Zynq7000 family contain any stored charge circuitry on the chip? The manual says there is "On-chip boot ROM", but is it mask-programmed...

Does the Zynq7000 family contain any stored charge circuitry on the chip? The manual says there is "On-chip boot ROM", but is it mask-programmed or flash? If there are flash cells, then what other SRAM-only ARM+FPGA chips should I look at? Best regards, Piotr


Scripts to maintain list of addresses in VHDL core communicating with SW via a set of control and status registers

Started by Wojciech M. ZaboŇāotny in comp.arch.fpga5 months ago 3 replies

Last time I had to prepare a firmware for FPGA, that contained a complex hierarchy of blocks and subbblocks, containing registers and arrays of...

Last time I had to prepare a firmware for FPGA, that contained a complex hierarchy of blocks and subbblocks, containing registers and arrays of registers on different levels of hierarchy. Those registers were connected to simple block driven by IPbus ( https://github.com/ipbus/ipbus-firmware ) or AXI-Lite slave (e.g., generated with Tools/Create and Package New IP/Ctreate AXI4 Peripheral), that pr...


Interface on board ADC to Spartan 3E startkit

Started by krunal in comp.arch.fpga5 months ago 15 replies

Hi, I want to interface on board ADC to spartan 3E startkit. Actually I am developing digital filter in FPGA for that I need ADC and...

Hi, I want to interface on board ADC to spartan 3E startkit. Actually I am developing digital filter in FPGA for that I need ADC and DAC interface with Spartan 3E. I have done with DAC but now I want to interface amplifier and ADC which are on board in Spartan 3E starter kit .........If any one have it's VHDL or Verilog code please give me..........Even I have find a document for imp...


Now - not so new cheaper FPGAs

Started by rickman in comp.arch.fpga6 months ago 4 replies

I have used the Lattice XP3 FPGAs in a design I've made a lot of money from. The parts have gone EOL but Arrow bought some 70,000+ and is...

I have used the Lattice XP3 FPGAs in a design I've made a lot of money from. The parts have gone EOL but Arrow bought some 70,000+ and is still trying to get rid of them. Seems they over estimated the market. I had to pay a higher price to them in 2016 than I paid when they were in production (~$10) but now they are going for around $5-$6 depending on quantity and they still have 65,...


Clock distribution /Resynchronizing

Started by Spehro Pefhany in comp.arch.fpga6 months ago 8 replies

Hi all, I would like to create and distribute a master clock and sync pulses to a number of boxes throughout a system. There will be some skew...

Hi all, I would like to create and distribute a master clock and sync pulses to a number of boxes throughout a system. There will be some skew between the signals, of unknown sign. Probably the clock will be 24.576MHz and sync will be in the kHz range. At the receiving nodes the clocks have to be de-jittered and preferably the two (or more) signals aligned with each other.


My invention: Coding wave-pipelined circuits with buffering function in HDL

Started by Weng Tianxiang in comp.arch.fpga6 months ago 42 replies

Hi, A wive-pipelined circuit has the same logic as its pipeline counterpart exc= ept that the wive-pipelined circuit has only one stage, a...

Hi, A wive-pipelined circuit has the same logic as its pipeline counterpart exc= ept that the wive-pipelined circuit has only one stage, a critical path fro= m the input register passing through a piece of computational logic to the = output register, and no intermediate registers. My invention kernel idea is: A designer provides the least information and = logic code about the critical ...


Qs on HDL library code and pipelining

Started by Julio Di Egidio in comp.arch.fpga6 months ago 4 replies

Hello everybody, and Happy New Year 2018! I am new to digital design, here are some basic questions: In particular for algorithm...

Hello everybody, and Happy New Year 2018! I am new to digital design, here are some basic questions: In particular for algorithm acceleration (e.g. arithmetic, cryptography, etc.), does it make sense to think both FPGA and ASIC when writing HDL library code? And, about pipelining combinational logic, what maximum gate-delay granularity would be good (for fmax) on FPGAs? I am guessing...


TinyFPGA Boards

Started by rickman in comp.arch.fpga6 months ago 3 replies

http://tinyfpga.com/ The web site does not work 100% as there are some broken links, but all the pages are there. They currently offer three...

http://tinyfpga.com/ The web site does not work 100% as there are some broken links, but all the pages are there. They currently offer three boards, A1/A2 provide two sizes of the Lattice XO2, the 256 and 1200. These two boards are basically just break out boards with nothing else other than decoupling caps and a ferrite bead. The B2 board uses the ICE40LP8K and comes with an SPI fla...


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