minimal HDMI pins to send video ?

Started by Anonymous in comp.arch.fpga4 months ago 7 replies

Dear all who knows 4 pairs of 1) CLOCK+, CLOCK- 2) TMDS2+, TMDS2- 3) TMDS1+, TMDS1- 4) TMDS0+, TMDS0- are enough to send video...

Dear all who knows 4 pairs of 1) CLOCK+, CLOCK- 2) TMDS2+, TMDS2- 3) TMDS1+, TMDS1- 4) TMDS0+, TMDS0- are enough to send video by HDMI or need to generate some other signals ?


What kit for SPARTAN-3?

Started by Borneq in comp.arch.fpga4 months ago

I have XILINX - XC3S4000 - 4FGG676I - SPARTAN-3 FPGA 4M STD 676-FBGA someone advise me XC6SLX9

I have XILINX - XC3S4000 - 4FGG676I - SPARTAN-3 FPGA 4M STD 676-FBGA someone advise me XC6SLX9


converting from Xilinx 9500 to 9500XL, won't fit

Started by Jon Elson in comp.arch.fpga4 months ago 2 replies

Hello, all, I have an old design implemented in the Xilinx 9572, and need to update it. Using ise 13.4, I created a new project, imported...

Hello, all, I have an old design implemented in the Xilinx 9572, and need to update it. Using ise 13.4, I created a new project, imported the files, and found it won't fit in the 9572XL, which was a big surprise. Although the 9572 was fairly full, the design easily fit there, and I just recompiled it for the 9572, and this version of ise easily fit it. Does anybody have any suggest...


IP core LCD controller for Zynq-7000 famiy

Started by Anonymous in comp.arch.fpga4 months ago

Do you know something about free IP cores for this fpga? Xylon IPs are too expensive for me. Cheers, ucy

Do you know something about free IP cores for this fpga? Xylon IPs are too expensive for me. Cheers, ucy


Ielts,Toefl, Pte, Esol, Toiec, Oet, Gmat, Gre, Nebosh, SAT, ACT, GED,

Started by velma niro in comp.arch.fpga5 months ago

Hi Friends You Have Problems in getting the required scores in Ielts,Toefl, Pte, Esol, Toiec, Oet, Gmat, Gre, Nebosh, SAT, ACT, GED,...

Hi Friends You Have Problems in getting the required scores in Ielts,Toefl, Pte, Esol, Toiec, Oet, Gmat, Gre, Nebosh, SAT, ACT, GED, Usmle, Psat, lsat, Celban, FCE, CAE,CPE, BEC, Fle, Tesol,??? Need Ielts certificate urgently in Australia, Saudi Arabia, Oman, Lebanon, Qatar, Canada, India, Dubai, Iran, Pakistan, Belarus, Kuwait, Germany, France, Anywhere... From British


consulting job / Xilinx Artix MGT POR

Started by Tobias Kahre in comp.arch.fpga5 months ago

Hi there, I am looking for an expert on how to by-hand-configure MGTs individually of an single quad. I have an Artix 35T, the first MGT has...

Hi there, I am looking for an expert on how to by-hand-configure MGTs individually of an single quad. I have an Artix 35T, the first MGT has to do aurora, the second and third one has to do JESD204b. I am offering a consulting fee for teaching me personally and/or working design of POR up to exchange of comma characters. Cheers, Tobias


VHDL or Verilog?

Started by Rick C. Hodgin in comp.arch.fpga5 months ago 20 replies

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use...

I've been given conflicting device on which language to use. There are people I would consider to be expert professionals who tell me to use VHDL, and others who tell me Verilog. Most everybody tells me that if I use VHDL there's less chance for error, but that it does take more effort to learn. Any thoughts? Thank you, Rick C. Hodgin


Create FPGA to replace 1974 MOSTEK MK5017

Started by Anonymous in comp.arch.fpga5 months ago 3 replies

Hi Everyone, Perhaps you may have a skill to create FPGA and create a clone for 1974 MOSTEK MK5017, famous clock chip by Heathkit. They used...

Hi Everyone, Perhaps you may have a skill to create FPGA and create a clone for 1974 MOSTEK MK5017, famous clock chip by Heathkit. They used this chip on model GC-1005 and run with Panaplex display tubes by Sperry Rand. Unfortunately, MOSTEK went out of business (thanks to US EPA that destroyed wonderful company by enormous fines instead of help to clean). Nowdays, it is impossib


Whups. Lattice Diamond says my package does not exist.

Started by Anonymous in comp.arch.fpga5 months ago 5 replies

Hi all. I'm stopped. Lattice Diamond does not offer a configuration for designing with my part in the 48-VFQFN package. The LCMXO2-640HC-6SG48I...

Hi all. I'm stopped. Lattice Diamond does not offer a configuration for designing with my part in the 48-VFQFN package. The LCMXO2-640HC-6SG48I is not available in the drop-down configuration menu. They say the closest they can get is the TQFP-100 or CSBGA-132 packages. My PCB and FPGA arrived days ago but I need a way to do development! Is there a way to configure Lattice Diamond


ZAP : An open source ARM processor (feedback)

Started by Anonymous in comp.arch.fpga6 months ago 19 replies

Hi, I am the author of the Gihub project ZAP ( https://github.com/krevanth/ZAP ). It is a 10-stage pipelined ARMv4T compatible soft processor...

Hi, I am the author of the Gihub project ZAP ( https://github.com/krevanth/ZAP ). It is a 10-stage pipelined ARMv4T compatible soft processor core with cache and memory management support. I developed it during my final semester in university. Would like your feedback/criticism of the project. Thanks, K Revanth


Ask a Question to the FPGARelated community

To significantly increase your chances of receiving answers, please make sure to:

  1. Use a meaningful title
  2. Express your question clearly and well
  3. Do not use this forum to promote your product, service or business
  4. Write in clear, grammatical, correctly-spelled language
  5. Do not post content that violates a copyright