Xilinx Platform cable USB and impact on linux without windrvr

Started by Michael Gernoth in comp.arch.fpga5 months ago 23 replies

Hello, after being bitten by windrvr once again (it did not compile after a kernel upgrade), I decided to see if I could get the Xilinx USB...

Hello, after being bitten by windrvr once again (it did not compile after a kernel upgrade), I decided to see if I could get the Xilinx USB cable and impact working without a kernel module. To achieve this, I have written a wrapper library for impact which maps calls to windrvr to the userspace libusb-library which should be available on all modern linux distributions. With this wrapper I...


Re: Help finding Xilinx software for HW-130 programmer

Started by Rob M in comp.arch.fpga5 months ago

responding to http://www.electrondepot.com/fpga/help-finding-xilinx-software-for-hw-130-programmer-81804-.htm , Rob M wrote: > TimRegeant ...

responding to http://www.electrondepot.com/fpga/help-finding-xilinx-software-for-hw-130-programmer-81804-.htm , Rob M wrote: > TimRegeant wrote: > > On 12/5/2016 10:37 PM, Joe Z wrote: > > responding to > > > http://www.electrondepot.com/fpga/help-finding-xilinx-software-for-hw-130-programmer-81804-.htm > > > > > , Joe Z wrote: > > > gnuarm wrote: > > > > > > On 5/3/2016 2:23


duty cycle of clock divider

Started by promach in comp.arch.fpga5 months ago 8 replies

http://www.fpga4fun.com/MusicBox1.html The frequency is 440Hz, as expected, but the output duty cycle is not 50% anymore. The low level goes...

http://www.fpga4fun.com/MusicBox1.html The frequency is 440Hz, as expected, but the output duty cycle is not 50% anymore. The low level goes from counter=0 to counter=32767 (when bit 15 of counter is low) and then high level from 32768 to 56817. That gives us "speaker" being high only 42% of the time. The easiest way to get a 50% duty cycle is to add a stage that divides the out


logic scope coding

Started by promach in comp.arch.fpga5 months ago 1 reply

Could anyone give general comments on https://github.com/promach/internal_logic_analyzer/tree/development/rtl ? Is my coding approach too...

Could anyone give general comments on https://github.com/promach/internal_logic_analyzer/tree/development/rtl ? Is my coding approach too software-centric ?


registers delay

Started by promach in comp.arch.fpga6 months ago 1 reply

for the case of registers dependencies, d

for the case of registers dependencies, d


Microsemi FPGAs

Started by John Larkin in comp.arch.fpga6 months ago 3 replies

Has anyone used the Microsemi SOCs, the SmartFusion2 FPGAs with an ARM Cortex M3 on chip? How good/awful is the tool set? Any big likes or...

Has anyone used the Microsemi SOCs, the SmartFusion2 FPGAs with an ARM Cortex M3 on chip? How good/awful is the tool set? Any big likes or dislikes? They look like a pretty good deal for a medium FPGA with ARM. -- John Larkin Highland Technology, Inc lunatic fringe electronics


Article about using Non-Project Mode

Started by Ilya Kalistru in comp.arch.fpga6 months ago 11 replies

Hi! During the discussion about "Test Driven Design?" I promised to write a paper about Non-Project Mode and how it helps with testing. The...

Hi! During the discussion about "Test Driven Design?" I promised to write a paper about Non-Project Mode and how it helps with testing. The problem is that I have never written any article. Moreover, English is not my native language. I kindly ask you to review the article and help me to improve it. It is in Google docs and leaving comments right in the document is allowed. You also can comment...


sram

Started by kristoff in comp.arch.fpga6 months ago 44 replies

Hi, OK, left the lora chips asside for a while, so .. now back to FPGAs. I have two olimex ice40 boards where I would like to use the...

Hi, OK, left the lora chips asside for a while, so .. now back to FPGAs. I have two olimex ice40 boards where I would like to use the onboard SRAM. The RAM chip is a samsung K5R4016V1B-10 (256K words * 16 bits). The datasheets are here: https://www.olimex.com/Products/_resources/ds_k6r4016v1d_rev40.pdf The most important pages are page 7 (for "read"), pages 8 and 9 (for "write") a...


Microsemi SmartFusion2 Field Upgrade

Started by Rob Gaddi in comp.arch.fpga6 months ago 4 replies

We're starting a new design, and I again find myself tempted by the Microsemi SmartFusion2 as combination FPGA/uC. It's got a built-in ARM...

We're starting a new design, and I again find myself tempted by the Microsemi SmartFusion2 as combination FPGA/uC. It's got a built-in ARM Cortex-M3, which is a simple dinky micro instead of some big honking A8 application processor that you can't even get up and running without kilobytes of boot code. The smallest, cheapest one is about $15 in small quantity with 64 kB of data memory ...


Suggestion on methodology/ways to test my internal logic analyzer softcore modules

Started by promach in comp.arch.fpga6 months ago

Using http://zipcpu.com/blog/2017/06/08/simple-scope.html , I have rewritten my internal logic analyzer at...

Using http://zipcpu.com/blog/2017/06/08/simple-scope.html , I have rewritten my internal logic analyzer at https://github.com/promach/internal_logic_analyzer I want to know if my softcore logic scope works. What inputs, into that module, and outputs from it will prove to me that my scope module works?


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