Hi all, I am trying to build a sequence detector to detect a decimal number like 10= 92 when a stream of numbers from 0-9 is given as input....

Hi all, I am trying to build a sequence detector to detect a decimal number like 10= 92 when a stream of numbers from 0-9 is given as input. Do you think just c= hanging the width of input i.e parallel inputs instead of series would resu= lt in pattern detection? I am lost in this, please help. If you have any re= sources around this do share them.

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. Is...

Hi, I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. Is there any software I can use to transform state machines in VHDL into drawings? Thank you. Weng

Hello everyone, I have recently started working on a project using Ethernet in an FPGA and I am using the UDP protocol for communication between...

Hello everyone, I have recently started working on a project using Ethernet in an FPGA and I am using the UDP protocol for communication between the PC and the FPGA. The communication is happening point to point so I was wondering do I need ARP implementation in my stack or can I just broadcast the message. I am building a UDP stack but was wondering is ARP a necessary requirement. Also, the ...

Hi, In the working process for my private project, I use free Notepad++ to code VHDL code and appreciate it very much! Here is an example of...

Hi, In the working process for my private project, I use free Notepad++ to code VHDL code and appreciate it very much! Here is an example of how powerful Notepad++ is: In 27 files, I easily found that I use the statement "when others => null; " 119 times and the statement "end case;" 117 times. There are certainly 2 mismatches for the 2 types of statements. I found only 1 mismat

CS302 – Digital Logic Design Graded Discussion Board You are required to program a PAL device to design a 64-bit counter. The stated...

CS302 – Digital Logic Design Graded Discussion Board You are required to program a PAL device to design a 64-bit counter. The stated PAL can be programmed using ABEL (Advanced Boolean Expression Language) and VHDL (Verilog Hardware Descriptive Language). Which programming technology would you use to accomplish the task outlined considering the constraints given below?

Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency? https://i.imgur.com/Rr1jS8Q.png...

Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency? https://i.imgur.com/Rr1jS8Q.png https://i.imgur.com/jgfvxk6.png

Hi, I have the following VHDL code for a state machine: type Output_State_t is ( State_a, State_b, State_c); signal...

Hi, I have the following VHDL code for a state machine: type Output_State_t is ( State_a, State_b, State_c); signal Output_State, Output_State_NS : Output_State_t ; At a clocked process, there is code with the Output_State: p1: process(Clock, Reset) begin if Reset then Output_State

Have anyone studied Pan's Algorithm previously ? http://people.eecs.berkeley.edu/~alanmi/publications/2005/iwls05_smr.pdf#page=3...

Have anyone studied Pan's Algorithm previously ? http://people.eecs.berkeley.edu/~alanmi/publications/2005/iwls05_smr.pdf#page=3 https://i.imgur.com/GO8s4BU.png 1. How is Pan's algorithm being a shortest-path algorithm when clock period is computed across the critical path (longest path) ? 2. Any idea about the modified version of Pan's algorithm described in Figure 2 on page ...

Most sorting algorithms I've noticed seem to have an interface somewhat like this: void someAlgorithm ( elemType[] elements); So to...

Most sorting algorithms I've noticed seem to have an interface somewhat like this: void someAlgorithm ( elemType[] elements); So to implement this algorithm an application needs to fill the {elements} array, call the {someAlgorithm()} algorithm, and then read out the (sorted) elements of {elements}. For an {elements} object that contains n {elemType}s, how long does it take to fi

Hi, I have a problem that does not do what is expected. I have several modules linked together from top to bottom. Each module has 3 error...

Hi, I have a problem that does not do what is expected. I have several modules linked together from top to bottom. Each module has 3 error output signals: Error_O, Error_Level_O, and Error_Code_O. If a module has an error, Error_O = '1', Error_Level_O and Error_Code_O have their proper error info. There are 3 arrays to correct that information from each of those modules: Error_O_m(), Error_...