pci-x133 to parallel pci-66

Started by Chad Bearden in comp.arch.fpga14 years ago 8 replies

I would like to split a pci-x133 bus into 2 parallel pci-66 busses. Has anyone done this? I'm not afraid to purchase the Xilinx pci-x core and...

I would like to split a pci-x133 bus into 2 parallel pci-66 busses. Has anyone done this? I'm not afraid to purchase the Xilinx pci-x core and halfbridge IP but just looking for some wisdom. |--------| | | | bridge | | |


PCI Slot Expansion

Started by Hui Li in comp.arch.fpga14 years ago 5 replies
PCI

I want to design a pci board which will expand one pci slot through a pci-bridge and pci-local bus and get two slot. I wonder if there is any...

I want to design a pci board which will expand one pci slot through a pci-bridge and pci-local bus and get two slot. I wonder if there is any driver problem? say i plug a audio card into the expanded slot? thanks Hui


PCI design with vhdl

Started by kender in comp.arch.fpga13 years ago 3 replies

Hi, I've read that many of you have realized PCI card using FPGAs... I have to do something similar, but I hope simpler, for my thesis (I'm an...

Hi, I've read that many of you have realized PCI card using FPGAs... I have to do something similar, but I hope simpler, for my thesis (I'm an university student): I have to realize a PCI core (but it should work as a target only device) that should transfer some data that is collected by the FPGA to an embedded processor, via the PCI bus... I "just" have to realize the PCI component for the...


PCI in a PCI-X slot

Started by Anonymous in comp.arch.fpga12 years ago 1 reply
PCI

I have a implemented a PCI 66Mhz master/target design on an Fpga, using an IP core from one of the well known suppliers. The core does...

I have a implemented a PCI 66Mhz master/target design on an Fpga, using an IP core from one of the well known suppliers. The core does not support PCI-X. The card works fine in 33Mhz and 66Mhz PCI slots. However, it sometimes fails to be seen by the PC when inserted in a PCI-X slot. I drive the PCIXCAP and M66EN pins on the card from the Fpga to signal that the card supports 66Mhz PCI bu...


PCI Card with FPGA

Started by Anonymous in comp.arch.fpga11 years ago 10 replies

Hi, I am looking for a PCI card with an FPGA on it with reasonable capacity of gates (15 million gates). I need to use this board as a...

Hi, I am looking for a PCI card with an FPGA on it with reasonable capacity of gates (15 million gates). I need to use this board as a hardware accelerator in a PC environment. My exact requirements for the PCI card are: 1. should have a PCI controller/ bridge on it so that I dont have to put PCI core on the FPGA. 2. the FPGA should be configurable through PCI (that means the programming p...


constraint for PCI & PCI-X core

Started by Anonymous in comp.arch.fpga13 years ago

Hi, I have a 100 MHz PCI-X core for Xilinx device. As a part of PCI-X standard the core is also compliant with PCI 33 MHz. Now I have a...

Hi, I have a 100 MHz PCI-X core for Xilinx device. As a part of PCI-X standard the core is also compliant with PCI 33 MHz. Now I have a problem with the ucf clock frequency constraint. Since I want it to work in PCI-X 100 MHz I constraint to clock of 100 MHz; but then the PCI 33 MHz logic fail to meet the timing constraints. I can identify the PCI 33 MHz critical paths as the path...


PCI arbiter doubt

Started by Anonymous in comp.arch.fpga12 years ago
PCI

Hi all, I have some basic doubts on PCI arbiter. 1)how is the framen controlled -- i guess it is a shared resource on the PCI bus wher...

Hi all, I have some basic doubts on PCI arbiter. 1)how is the framen controlled -- i guess it is a shared resource on the PCI bus wher all the devices sitting on the PCI bus have access to it. 2)If a request is received from a device on PCI bus ,should the grant be issued immediately or should the PCI arbiter wait until the framen is dropped (asserted). 3)If a request is rece...


Xilinx Spartan II and 5V PCI

Started by Christian E. Boehme in comp.arch.fpga13 years ago 16 replies

Hello all, I am using a Xilinx Spartan II FPGA on a prototype PCI add-in card as the PCI device attached to the bus. According to the Spartan...

Hello all, I am using a Xilinx Spartan II FPGA on a prototype PCI add-in card as the PCI device attached to the bus. According to the Spartan II data sheet it appears that 5V PCI compatible IOs are indeed instantiable which was the very reason for going with a Spartan II in the first place. However, after correlating the appropriate requirements from the PCI spec with what is claimed in...


References to good PCI boards and some newbie questions - please help!

Started by Valery in comp.arch.fpga14 years ago 1 reply

Hi, we are starting a project in our group porting several CPU intensive but simple apps to FPGA platform. We have selected PCI as a way...

Hi, we are starting a project in our group porting several CPU intensive but simple apps to FPGA platform. We have selected PCI as a way to communicate with a host PC. We have some experience programming FPGAs but not PCI-based (need PCI now due to data transfer speed requirements). I would be very grateful if someone can answer the folowing for us: 1. What PCI boards you would recomm...


embedded PCI

Started by colin in comp.arch.fpga13 years ago 6 replies

I would like to embed a device that has a PCI inteface with an FPGA (preferably a SPARTAN 3). Two questions have arisen before I start 1)...

I would like to embed a device that has a PCI inteface with an FPGA (preferably a SPARTAN 3). Two questions have arisen before I start 1) Many PCI based chips (including the one I want to use) can be purchased as a PCI card to speed up development. I have had a good google without success but does anyone know of an FPGA development platform that includes a PCI card site, I could then dev...


pci protocol analyzer

Started by Chad Bearden in comp.arch.fpga14 years ago 1 reply
PCI

Could anyone recommend a tool for analyzing the pci or pci-x protocol? I'm developing a pci-x board that will plug into a pc architecture. ...

Could anyone recommend a tool for analyzing the pci or pci-x protocol? I'm developing a pci-x board that will plug into a pc architecture. I have googled around and found several manufacturers but am looking for testimonials from those that have actually used such products and would comment on their usability and features. chad.


Host-PCI Bridge

Started by naveen in comp.arch.fpga14 years ago 3 replies

Hi group, I had a small clarification on Host-PCI Bridge. For Host-PCI bridge design, PCI 2.3 specs. itself are enough or PCI-PCI...

Hi group, I had a small clarification on Host-PCI Bridge. For Host-PCI bridge design, PCI 2.3 specs. itself are enough or PCI-PCI Bridge specs. are needed? Also in case of a Host-PCI Bridge, can we have Memory Read line, Memory Read Multiple, Memory write and invalidate commands executed? If we need to implement them do we need larger fifo inside the bridge? Minimum of how many fif...


Strange Spartan2 behaviour

Started by Nico Coesel in comp.arch.fpga9 years ago 10 replies
PCI

I'm working on a Spartan2 design which runs on a PCI card or a PCI Express card (through a PCI-express to PCI bridge chip). Besides the PCI...

I'm working on a Spartan2 design which runs on a PCI card or a PCI Express card (through a PCI-express to PCI bridge chip). Besides the PCI express or PCI interface the design is almost the same for both boards. In some specific type of PCs (mostly server chassis) the design quits working right away or after a while. Some of the internal statemachines quit even when the option 'Safe implem...


PCI newbie problems

Started by Massi in comp.arch.fpga9 years ago 5 replies

Hi everyone, I'm trying to set up a toy design on a Xilinx Virtex 5 (Avnet PCI Express Development Kit board) and I'm having big problems...

Hi everyone, I'm trying to set up a toy design on a Xilinx Virtex 5 (Avnet PCI Express Development Kit board) and I'm having big problems to understand how PCI works. I downloaded the PCI endpoint core bitstream for the Programmed IO on the board and plugged it into a pc, everything seems to work fine as a matter of fact PCI tree succeeds in recognizing the board. My aim now is really simp...


Re: FPGA : PCI core needed

Started by Kevin Brace in comp.arch.fpga12 years ago

Hi bijoy, My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI IP core called BDS...

Hi bijoy, My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI IP core called BDS XPCI PCI IP core. Assuming that your project's PCI interface is target only (no initiator), and uses only one BAR (Base Address Register), BDS XPCI32 PCI IP core should occupy roughly 580 LUTs and 250 FFs. That should translate roughly 290 Slices (580...


Re: FPGA : PCI core needed

Started by Kevin Brace in comp.arch.fpga12 years ago

Hi bijoy, My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI IP core called BDS XPCI...

Hi bijoy, My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI IP core called BDS XPCI PCI IP core. Assuming that your project's PCI interface is target only (no initiator), and uses only one BAR (Base Address Register), BDS XPCI32 PCI IP core should occupy roughly 580 LUTs and 250 FFs. That should translate roughly 290 Slices (580 / ...


Re: FPGA : PCI core needed

Started by Kevin Brace in comp.arch.fpga12 years ago

Hi bijoy, My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI IP core called BDS XPCI...

Hi bijoy, My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI IP core called BDS XPCI PCI IP core. Assuming that your project's PCI interface is target only (no initiator), and uses only one BAR (Base Address Register), BDS XPCI32 PCI IP core should occupy roughly 580 LUTs and 250 FFs. That should translate roughly 290 Slices (580 / ...


FPGA : PCI core needed

Started by Kevin Brace in comp.arch.fpga12 years ago 4 replies

Hi bijoy, My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI IP core called BDS XPCI...

Hi bijoy, My company Brace Design Solutions has developed a Xilinx (TM) LogiCORE (TM) PCI compatible (replacement) PCI IP core called BDS XPCI PCI IP core. Assuming that your project's PCI interface is target only (no initiator), and uses only one BAR (Base Address Register), BDS XPCI32 PCI IP core should occupy roughly 580 LUTs and 250 FFs. That should translate roughly 290 Slices (580 / ...


Writing PCI constraints in Altera

Started by tushit in comp.arch.fpga13 years ago 9 replies

Hi, I am fairly new to FPGAs. I am trying to write the constraints for the PCI module on an Altera Stratix device. I am using QuartusII for...

Hi, I am fairly new to FPGAs. I am trying to write the constraints for the PCI module on an Altera Stratix device. I am using QuartusII for all synthesis and P&R. The PCI spec says I need to ensure a setup time of 7ns for all pins. The PCI clock itself works at 33Mhz. I want to know the following: 1) Is it okay if I just constraint the PCI clk of my design to 50Mhz (30ns for the 33Mhz clock...


Data buffering scheme problem for PCI-E interface

Started by vcar in comp.arch.fpga8 years ago 5 replies

I want to capture data from an ADC and send to PC though PCI-E. I prefer using the Virtex5 XC5VLX20T-FF323 to implement the PCI-E Lane X4...

I want to capture data from an ADC and send to PC though PCI-E. I prefer using the Virtex5 XC5VLX20T-FF323 to implement the PCI-E Lane X4 interface. I need real time data capturing, and the input data rate is about 500Mbytes per second. Although the PCI-E X4 could provide a data channel of about 800Mbytes per second (based on the Xilinx ML555 PCI-E X4 experiment data), I am afraid that if the...