VHDL or verilog

Started by CMOS in comp.arch.fpga14 years ago 8 replies

hi, ive completed a introductory book on vhdl, but not mature enough to do a real world complex designs using vhdl. i've been serching...

hi, ive completed a introductory book on vhdl, but not mature enough to do a real world complex designs using vhdl. i've been serching for tutorial guids to learn advanced vhdl, preferebly with case studies, but found non. most of the books on vhdl are introductory level. Some advanced vhdl books such as "The Designer's Guide to VHDL" does not consider sysnthesis aspect much. beacause of thi...


RFC: VHDL testbench enhancements

Started by Jim Lewis in comp.arch.fpga13 years ago 5 replies

Hi, Let me try this again. The VHDL standards community has been considering whether to enhance VHDL to add advanced testbench...

Hi, Let me try this again. The VHDL standards community has been considering whether to enhance VHDL to add advanced testbench features. If you are a VHDL user, Do you want these features added to VHDL? Would you rather adopt a verification language that already supports these (SystemVerilog, SystemC, E, Vera). I think VHDL needs these features to stay competitive. The cu...


RFC: Enhancing VHDL for OO, Randomization, Functional Coverage

Started by Jim Lewis in comp.arch.fpga13 years ago 4 replies

Hi, The VHDL standards community needs feedback from VHDL users. Currently the Accellera VHDL TSC is working on enhancements to add...

Hi, The VHDL standards community needs feedback from VHDL users. Currently the Accellera VHDL TSC is working on enhancements to add classes/OO, Randomization constructs, and Functional Coverage with a goal of giving VHDL the same verification capability as SystemVerilog or E. One of the VHDL simulation vendors has indicated that they only want to implement new features if the user commu...


configuration for a mixed mode VHDL-verilog lang

Started by Rakesh YC in comp.arch.fpga16 years ago 1 reply

Hi all My problem is I'd like to choose a VHDL file instantiated inside verilog via VHDL configuration To summerize: I have a hierarcy:...

Hi all My problem is I'd like to choose a VHDL file instantiated inside verilog via VHDL configuration To summerize: I have a hierarcy: "top:vhdl - verilog - Verlog -vhdl: bottom" How to write a vhdl configuration to select the file for the bottom instantiation? Rakesh YC


Combining Schematic and VHDL code in Webpack 8.1 ??

Started by Per Jensen in comp.arch.fpga14 years ago 2 replies

Hello! I am a beginner in VHDL programming. i am programming an Xilinx XC9572XL at the moment, and i have so far used VHDL programming. I...

Hello! I am a beginner in VHDL programming. i am programming an Xilinx XC9572XL at the moment, and i have so far used VHDL programming. I am a little bit unsure, if i can combine VHDL and Shcematic, so a part of the circuit is described by Schematic, and another by VHDL. Is it possible, and how do i "bind" these things together ?? When i add a new source as an Schematic and compile, ...


Using VHDL packages

Started by kami in comp.arch.fpga12 years ago 4 replies

Hey there, I have asked this question in another forum as well but that forum has gone into the 2nd page and I am not sure how many people would...

Hey there, I have asked this question in another forum as well but that forum has gone into the 2nd page and I am not sure how many people would bother going to the next page. Anyways, I am trying to implement IIR filter in VHDL. And for that purpose, I need to use Fixed point arithematic. Now, I came accross the VHDL Fixed point packages available at: http://www.vhdl.org/vhdl-200x/vhdl...


VHDL gate level from Xilinx XST

Started by Laurent Gauch in comp.arch.fpga16 years ago 1 reply

Hi all, I need to generate a part of my VHDL project as a VHDL gate level IP, in the goal to protect my generic IP core. In fact, I want...

Hi all, I need to generate a part of my VHDL project as a VHDL gate level IP, in the goal to protect my generic IP core. In fact, I want to protect my own PCI core before delivering the complet VHDL project. My question: Is this possible to do a VHDL gate level Netlist from XST. Then to remap it in my VHDL project. Then to do a concatenated VHDL file of by project . Then do a new ...


Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments

Started by Kutaj Vamor in comp.arch.fpga15 years ago 5 replies

Dear FPGA and VHDL Experts, I am new to FPGA and VHDL. I would like to learn VHDL and start experimenting FPGA. I beleive I learn faster and...

Dear FPGA and VHDL Experts, I am new to FPGA and VHDL. I would like to learn VHDL and start experimenting FPGA. I beleive I learn faster and better by experimenting. What would you recommend for beginners like me to getting started with VHDL and FPGA experimentation ? Which SW (for WinXP and/or Fedora Linux ) for VHDL? Which start-up experimentation board for FPGA? Which URL, books etc ...


from VHDL to FPGA

Started by elesser in comp.arch.fpga14 years ago 6 replies

Hi everyone, I'm a student electronics and computer engineering, and I've already got quite a bit of experience with hardware design in...

Hi everyone, I'm a student electronics and computer engineering, and I've already got quite a bit of experience with hardware design in general and with VHDL. I was wondering if someone knows a good reference or book that explains what the VHDL compiler actually does with the code, to convert it into logic and put it into the FPGA. In other words, how is a VHDL compiler created, how doe...


VHDL modelling USB device

Started by ALuPin in comp.arch.fpga16 years ago 2 replies

Hi VHDL folks, does somebody know if there are VHDL models available for USB devices ? A simple model (behavioral) would do the job. Any...

Hi VHDL folks, does somebody know if there are VHDL models available for USB devices ? A simple model (behavioral) would do the job. Any hints are appreciated. Thank you for your help. Rgds


VHDL comments in Vim?

Started by Peter Sommerfeld in comp.arch.fpga16 years ago 5 replies

Hi folks, I'm getting tired of commenting large blocks of VHDL code by hand. Anyone know of any Vim scripts that can comment/un-comment a...

Hi folks, I'm getting tired of commenting large blocks of VHDL code by hand. Anyone know of any Vim scripts that can comment/un-comment a VHDL block? A cursory Google search brings up either nothing or way too much stuff to sift through depending on my search terms ("vhdl vim comment"). -- Pete


Info request about Synplify and Foundation usage

Started by Anonymous in comp.arch.fpga12 years ago 1 reply

Dear all, I'm try to use VHDL code with some old XC5202PQ100-6 part that I've from my old design. Old design was did by using Foundation 2.1i...

Dear all, I'm try to use VHDL code with some old XC5202PQ100-6 part that I've from my old design. Old design was did by using Foundation 2.1i and Schematic Entry, now I'm searching a way to use the VHDL coding to do some simple example and learn VHDL. My Foundation tools was only a base installation then I don't have the Express feature then no VHDL compiler will available, but I've the Synp...


Code blocks to realize this in VHDL

Started by mstanisz in comp.arch.fpga11 years ago 1 reply

I've searched a little more and found that if I can somehow merge Ben Cohen's 0 ohm...

I've searched a little more and found that if I can somehow merge Ben Cohen's 0 ohm device (http://groups.google.com/group/comp.lang.vhdl/msg/7d14832588a0cabb) with a bi-directional MUX (http://www.tek-tips.com/viewthread.cfm?qid=1188582&page=7), then I might be able to create the VHDL module I would need. The bus splitting doesn't need a module, since in VHDL I'll just manipulate bit0 of the inp...


VHDL and Latch

Started by Weng Tianxiang in comp.arch.fpga13 years ago 35 replies

Hi, I am very confused with latch generation in VHDL. 1. I have been using VHDL for 7 years and I have never met a situation I need a...

Hi, I am very confused with latch generation in VHDL. 1. I have been using VHDL for 7 years and I have never met a situation I need a latch. 2. I want to know why VHDL let VHDL programmers guess what is to be generated in the following situation that I know is only case a latch may be generated: process(a, ...) begin -- signalA i


AWGN in VHDL

Started by MACEI'S in comp.arch.fpga17 years ago 4 replies

Hi guys, Does anybody have any idea or any link or code for Additive White Gaussian Noise in VHDL ? Or any body have written it or not...

Hi guys, Does anybody have any idea or any link or code for Additive White Gaussian Noise in VHDL ? Or any body have written it or not ? Also how to generate Random Number's in VHDL? Thanks Rgds Macie


VHDL to Verilog Converter

Started by Ambreen Ashfaq Afridi in comp.arch.fpga12 years ago 3 replies

Hi im looking for a vhdl to verilog converter. Im working with Trimode Ethernet MAC core which is written in VHDL. I have to modify this...

Hi im looking for a vhdl to verilog converter. Im working with Trimode Ethernet MAC core which is written in VHDL. I have to modify this code but the problem is that I dont have any knowledge of VHDL. I do programming in Verilog.Plz send me any link for the converter. Thank you Regards, Ambreen Ashfaq


JOP VHDL simulation

Started by Martin Schoeberl in comp.arch.fpga15 years ago 1 reply

VHDL level simulation of JOP is now available ;-) The actual version of JOP at the usual download...

VHDL level simulation of JOP is now available ;-) The actual version of JOP at the usual download page http://www.jopdesign.com/download.jsp now contains (hopefully) all necessary file to run a simulation with ModelSim or a different VHDL simulator. In directory vhdl/simulation you will find: * A test bench: tb_jop.vhd with a serial receiver to print out the messages from...


Writing VHDL, Software dummy!

Started by Anonymous in comp.arch.fpga14 years ago 5 replies

I have a couple of questions regarding VHDL and FPGAs as I am starting a project on them shortly0. Before I start I would like to...

I have a couple of questions regarding VHDL and FPGAs as I am starting a project on them shortly0. Before I start I would like to apologize for my lack of knowledge on them. I am a software developer not a hardware so you might have to take this into consideration when explaining. I know VHDL is a hardware description language, but what is the biggest challenge when writing code in VHDL...


Altera and VHDL library

Started by Clemens Hermann in comp.arch.fpga15 years ago 6 replies

Hi, with the latest quartus II software I created two VHDL packages. After testing the packages I wanted to combine them in a custom VHDL...

Hi, with the latest quartus II software I created two VHDL packages. After testing the packages I wanted to combine them in a custom VHDL library with no success. My goal is to have a directory that contains the library (preferrably precompiled) so that I can pass it around and it could be used by others as simple as the standard VHDL libraries (e.g. ieee) like LIBRARY my_lib; USE my_l...


Need help with VHDL simulation with SPW in Linux

Started by dang...@yahoo.com in comp.arch.fpga13 years ago

Hi every one. I am newbie in FPGAs, although I can write VHDL. I already setup a copy of Cadence SPW 4.82 from my company to study FPGA...

Hi every one. I am newbie in FPGAs, although I can write VHDL. I already setup a copy of Cadence SPW 4.82 from my company to study FPGA myself. My OS is Scientific Linux 3.08 (clone of Redhat Enterprise 3.x). My purpose is to design in SPW by using fixed-pointed HDS, and generate to VHDL to FPGA board (etc. Xilinx). SPW can support co-simulation with C/C++ and VHDL, and I have some exper...