Does XST support global signals?

Started by EM in comp.arch.fpga9 years ago 4 replies

Hello folks, I searched this newsgroup, Xilinx's website, and the XST user's guide, but I couldn't find what I was looking for. Does...

Hello folks, I searched this newsgroup, Xilinx's website, and the XST user's guide, but I couldn't find what I was looking for. Does anyone know if XST supports global nets? In my last project I used Synplicity, which allowed me to use global nets / buses. In this new project I'm using XST. XST itself doesn't complain, but I'm getting goofy errors with NGDBUILD. I'm just wonderin...


XST optimization

Started by Jason Thibodeau in comp.arch.fpga7 years ago 11 replies
XST

Is it possible to get a detailed report out of XST, listing the gates it has optimized out of a design? XST is removing some gates that I...

Is it possible to get a detailed report out of XST, listing the gates it has optimized out of a design? XST is removing some gates that I specifically put into a design, and I want to prevent this. I can use the XST constraints file, but I'd like to see exactly what it is doing. Googling hasn't turned up much, yet. Thanks -- Jason Thibodeau


XST vs Synplify

Started by Anonymous in comp.arch.fpga12 years ago 3 replies

Hi all, I wish to have an idea about how many people here uses Synlify or Leonardo and how many people uses XST. The purpose of that is...

Hi all, I wish to have an idea about how many people here uses Synlify or Leonardo and how many people uses XST. The purpose of that is undesrtand how many people here beleave that XST is a mature product and it can be trusted or not. At moment I'm tryng to use XST for a small FPGA (spartan 2E 150) and I'm having a lot of trouble. (I have several years of experience and I made design very c...


XST Question

Started by Naimesh in comp.arch.fpga13 years ago 4 replies
XST

How do I buffer a signal in XST as I feel it is getting overloaded. if I write Signal1

How do I buffer a signal in XST as I feel it is getting overloaded. if I write Signal1


Xst Error

Started by Ramakrishnan in comp.arch.fpga12 years ago 1 reply

Hi, I was trying to implement my design in Xilinx ISE using Xst as the Synthesis tool. It gave me a error INTERNAL_ERROR:Xst:cmain.c:3020:1.146 -...

Hi, I was trying to implement my design in Xilinx ISE using Xst as the Synthesis tool. It gave me a error INTERNAL_ERROR:Xst:cmain.c:3020:1.146 - To resolve this error, please consult the Answers Database and other online resources at . To give you a basic idea, my program is IF Generate Structures and my guess is this is causing the Xst to crash. I am unable to find any


Generics of type time and XST synthesis

Started by Brandon in comp.arch.fpga12 years ago 1 reply
XST

I'm new to FPGA synthesis and XST, so I could use some help. I'm synthesizing an entity for the first time, and I'm receiving warnings and...

I'm new to FPGA synthesis and XST, so I could use some help. I'm synthesizing an entity for the first time, and I'm receiving warnings and errors related to the time type in my models. I realize that they are not synthesizable. I'm okay with the warnings because I have them in there for functional simulation only. Here is the output from XST in Foundation 7.1: WARNING:Xst:828


Inferring Dynamic shift registers in XST

Started by Josh Graham in comp.arch.fpga13 years ago 8 replies

Hello all, I am trying to get XST (ISE 6.1) to infer a dynamic shift register implemented using Virtex II LUTS. I have used the VHDL model...

Hello all, I am trying to get XST (ISE 6.1) to infer a dynamic shift register implemented using Virtex II LUTS. I have used the VHDL model shown below. However XST does not use LUTS, instead flip-flops are used. When I change the line srout


XST returning error code on success?

Started by Dom Bannon in comp.arch.fpga7 years ago 5 replies

I'm just taking over someone else's project and am running it on Cygwin/ISE 12.4 (it was previously building correctly on Linux/12.3). I'm...

I'm just taking over someone else's project and am running it on Cygwin/ISE 12.4 (it was previously building correctly on Linux/12.3). I'm building with a makefile; the first 2 steps are XST, then ngdbuild. 'make' reports that XST fails with an exit code of 1, but XST has actually produced ngc and syr files. The syr file reports no errors, and a few hundred warnings and infos. If I ignore ...


Define the primary clock with XST in VHDL

Started by Julien Lochen in comp.arch.fpga10 years ago 2 replies

Hello Guys, How to specify with XST that an input of a VHDL entity is a clock ? I guess it is not automatic because after the XST logic...

Hello Guys, How to specify with XST that an input of a VHDL entity is a clock ? I guess it is not automatic because after the XST logic synthesis, noone of my "process" have been synthetized ? thanks, Julien


XST broken for XC9536?

Started by Andreas Ehliar in comp.arch.fpga11 years ago 7 replies

I was a TA for an introductory VHDL lab yesterday and I encountered a very weird problem. In the source code included below I get the following...

I was a TA for an introductory VHDL lab yesterday and I encountered a very weird problem. In the source code included below I get the following interesting messages from XST when I try to synthesize the file: INFO:Xst:1799 - State start is never reached in FSM . INFO:Xst:1799 - State stop is never reached in FSM . INFO:Xst:1799 - State data_1 is never reached in FSM .


XST and TCL support?

Started by Brandon in comp.arch.fpga12 years ago 6 replies

Does XST 7.1 support TCL scripting? I don't see any mention of it in the XST User Manual and I find the command line mode to be very awkward...

Does XST 7.1 support TCL scripting? I don't see any mention of it in the XST User Manual and I find the command line mode to be very awkward performing synthesis using the GUI or command line without a script. I'm new to XST, and I'm looking for ways to organize my synthesis process. By default the tool dumps all of synthesis files all over the place, ugh. I was hoping I could have some ...


XST and Verilog $readmemh

Started by johnp in comp.arch.fpga10 years ago 1 reply

In theory, XST claims to support the Verilog $readmemh to initialize memory. I'm using the latest 9.x s/w verion. I look at the .syr output...

In theory, XST claims to support the Verilog $readmemh to initialize memory. I'm using the latest 9.x s/w verion. I look at the .syr output file from XST, and it claims to have read the file. But... If I hook a logic analyzer up to the output of the memory, it looks like it never got initialized. Another problem I'm seeing is that XST appears to not like having an address line (@...


XST Internal error: VHDL constant record support

Started by Anonymous in comp.arch.fpga11 years ago 3 replies

Hi All, Just wanted to know if anyone has experienced any problems with Xilinx XST when declaring a constant record in VHDL. Below is...

Hi All, Just wanted to know if anyone has experienced any problems with Xilinx XST when declaring a constant record in VHDL. Below is some, what I hope to be valid, VHDL, that makes XST fail and spit out a Internal Error. I'm using ISE 7.1 (SP4) running on a Linux Box. Is this really an XST bug/problem/deficiency? Would be great to hear from any 8.1 users to see if this is still a p...


xst fails...

Started by Matthias Alles in comp.arch.fpga10 years ago 6 replies

Hi, I'm currently trying to synthesize a big design on a Virtex4-VLX100. Now the problem is, that xst fails and just gives the following...

Hi, I'm currently trying to synthesize a big design on a Virtex4-VLX100. Now the problem is, that xst fails and just gives the following line: Process "Synthesize" failed Is there a way to hunt for the problem that causes this behavior? I'm a little bit lost, since there is no hint by xst. Thanks, Matthias


DSP48 Inference Template for XST

Started by Kevin Neilson in comp.arch.fpga9 years ago 1 reply
XST

I'd like to infer a DSP48 in XST and can't find a template that will infer all of these opmodes: P=M P=M+C P=P+M P=P-M (where...

I'd like to infer a DSP48 in XST and can't find a template that will infer all of these opmodes: P=M P=M+C P=P+M P=P-M (where M=A*B) I can get XST to do any of these, one or two at a time, but when I try to do all at once it adds a bunch of fabric. Any suggestions? The code below, for example, properly connects up the ALUMODE pins (in a V5) for the add/subtract function, b...


Xilinx XST 6.x and Verilog-2001?

Started by Allan Herriman in comp.arch.fpga14 years ago 1 reply

Hi, Does Xilinx XST 6.x support RTL-synthesis of Verilog-2001? This...

Hi, Does Xilinx XST 6.x support RTL-synthesis of Verilog-2001? This document http://toolbox.xilinx.com/docsan/xilinx5/data/docs/xst/xst0083_11.html shows that the older version, XST 5.x, has partial support for Verilog 2001. I was wondering if the support is better in the newer version of ISE. In particular, I'm interested in knowing if 'generate' works, and whether arrays of inst...


XST Help - Device Utilization Woes

Started by Brandon in comp.arch.fpga12 years ago 9 replies

Hello, I'm synthesizing a design in XST and I'm having a hard time figuring out what's consuming all of the devices resources. I wrote...

Hello, I'm synthesizing a design in XST and I'm having a hard time figuring out what's consuming all of the devices resources. I wrote mostly structural VHDL, so I decided to synthesize each component separately to get a better idea of the low level utilization. I haven't seen any option in XST to see a hierarchal analysis of area... Anyway, I estimated the resource consumption of my des...


XST crashes & websupport denies access

Started by Tommy Thorn in comp.arch.fpga11 years ago

Sorry for the uninteresting post, but I was trying my Altera design in ISE 8.1i and XST crashed immediately with ...

Sorry for the uninteresting post, but I was trying my Altera design in ISE 8.1i and XST crashed immediately with FATAL_ERROR:Xst:Portability/export/Port_main.h:127:1.16 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate etc. I tried to file a WebSupport case, but I can kind of understand the previous rant thread here as it is ...


XST pre-defined macros

Started by Jeff Brower in comp.arch.fpga11 years ago

All- Does XST provide any pre-defined macros or constants? For example: __BUILD_NUMBER __XST_VER that could be used in source code...

All- Does XST provide any pre-defined macros or constants? For example: __BUILD_NUMBER __XST_VER that could be used in source code as contents of a logic revision register, or could be used to know which version of XST is in use? If this is not available, is there a way to kludge it that's "relatively automatic"? To Xilinx: I know that "ISE ain't Visual Studio", but helpful...


Re: XST synthesis

Started by B. Joshua Rosen in comp.arch.fpga13 years ago 6 replies

On Sat, 21 Aug 2004 18:08:26 +0000, Simon wrote: > Was wondering if anyone would be kind enough to help me out here - I've been > struggling...

On Sat, 21 Aug 2004 18:08:26 +0000, Simon wrote: > Was wondering if anyone would be kind enough to help me out here - I've been > struggling with a synthesis problem in Webpack, and would appreciate being > pointed in the right direction :-) > > XST is telling me: > > WARNING:Xst:528 - Multi-source in Unit on signal not > replaced by logic > Sources are: data 5:dat