Embedded Design Handbook
The Embedded Design Handbook complements the primary documentation for the Altera® tools for embedded system development. It describes how to most effectively use the tools, and recommends design styles and practices for developing, debugging, and optimizing embedded systems using Altera-provided tools. The handbook introduces concepts to new users of Altera’s embedded solutions, and helps to increase the design efficiency of the experienced user.
Summary
The Embedded Design Handbook (Altera, 2011) explains how to use Altera/Intel development tools and recommended design practices for embedded FPGA systems. The handbook teaches workflows for composing, debugging, and optimizing embedded SoCs (including guidance on Nios II, toolflows, and HLS techniques).
Key Takeaways
- Apply Altera-recommended toolflows and design styles to accelerate embedded FPGA development and system integration.
- Compose and connect IP and processors using Platform Designer (Qsys) and Quartus workflows for robust SoC builds.
- Optimize hardware/software partitioning and accelerate datapaths using High-Level Synthesis techniques and FPGA-aware optimizations.
- Debug and profile embedded designs with JTAG, SignalTap, and software-side debugging methods to reduce bring-up time.
Who Should Read This
FPGA embedded designers and firmware engineers with some FPGA tool experience who want practical guidance on Altera/Intel tool usage, system integration, and optimization.
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