Implementing the Nintendo Entertainment System on a FPGA

Jonathan Sieber

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In this work I try to implement the Nintendo Entertainment System (NES) on a FPGA platform. The NES is one of the most famous video game consoles of the 8-bit era. Using custom designed hardware that was primarily optimized for low cost, and was not very powerful at that time, it still was the basis for a big library of high quality games, that are still fun to play today. Besides being a practical exercise in hardware design, this project aims to be a continuation of the efforts of the emulator scene, to conserve video game history by bringing it to new hardware platforms.

Summary

This paper documents an effort to reproduce the Nintendo Entertainment System on an FPGA, describing how the NES CPU, PPU, memory, and cartridge logic can be mapped to reconfigurable hardware. Readers will learn practical design decisions, implementation challenges, and trade-offs when recreating an 8-bit console with Verilog/SystemVerilog on modern FPGAs.

Key Takeaways

Map the NES 6502-derived CPU and PPU functions into modular, FPGA-friendly HDL components.
Implement cycle-accurate behavior or acceptable approximations for CPU/PPU interactions to preserve game compatibility.
Design tile and sprite rendering logic plus scanline/NTSC timing to produce correct video output on FPGA hardware.
Manage cartridge/ROM interfacing and mapper (bank-switching) logic to support diverse game cartridges.
Address timing closure and resource trade-offs for target Xilinx/AMD devices to meet video and audio timing constraints.

Who Should Read This

FPGA designers and hardware hobbyists with HDL experience who want to learn practical techniques for implementing retro game consoles and mapping their subsystems to FPGA logic.

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