Summary

This blog explains how to use a digital phase-locked loop (DPLL) on an FPGA to lock a digital oscillator to a 1PPS (One Pulse Per Second) reference from a GPS receiver. It guides the reader through the DPLL architecture, implementation choices in Verilog/SystemVerilog, and practical issues such as jitter, loop tuning, and clock-domain handling.

Key Takeaways

• Design a DPLL architecture that locks an NCO/DCO to an external 1PPS reference.
• Implement phase detection, loop filtering, and frequency correction in Verilog/SystemVerilog.
• Apply coarse and fine control strategies to correct frequency and minimize jitter.
• Manage clock domain crossing and edge capture between the high-rate oscillator and the low-rate 1PPS domain.
• Tune loop gains and evaluate stability and lock time through jitter and phase-noise analysis.

Who Should Read This

FPGA/embedded engineers with HDL experience who need to synchronize a local oscillator to GPS 1PPS for timing, measurement, or data-acquisition applications.

Still RelevantIntermediate

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