Is it possible to write a test bench using VHDL in Quartus? When I tried I got an error message telling me that wait <n> construct is not supported. Is that true or am I making some mistake? Is there any way, may be using tcl, I can simulate a VHDL like test bench? Testbench using waveforms just does not work for me. Thanks. Pratip Mukherjee pratipm.remove_this@hotmail.com
VHDL test bench in Quartus
Started by ●May 28, 2004
Reply by ●May 28, 20042004-05-28
Pratip Mukherjee <pkm11@hotmail.com> wrote in message news:<Xns94F78EDBFB5E2PratipMukherjee51@216.148.227.77>...> Is it possible to write a test bench using VHDL in Quartus?No. Use modelsim or sonata. -- Mike Treseler
Reply by ●June 3, 20042004-06-03
My guess, is that Quartus only supports synthesizeable VHDL and wait is not synthesizeable. If I not mistake, you have only the waveform program to create testbenches, and so I use Modelsim for my simulations of Altera-targeted designs. Salman Pratip Mukherjee wrote:> Is it possible to write a test bench using VHDL in Quartus? When I tried I > got an error message telling me that wait <n> construct is not supported. > Is that true or am I making some mistake? Is there any way, may be using > tcl, I can simulate a VHDL like test bench? Testbench using waveforms just > does not work for me. > Thanks. > > Pratip Mukherjee > pratipm.remove_this@hotmail.com
Reply by ●June 3, 20042004-06-03
There is something missing in this discussion. If you are talking about testbenches, then Quartus can't help you since testbenches are used in simulations and Quartus is not a VHDL simulator. I agree that using waveforms to simulate FPGA designs is not desirable. That is why I write my code to run on either Altera or Xilinx devices and use the Xilinx Modelsim simulator to test my design. I then fit the same design to the Altera devices. salman sheikh wrote:> > My guess, is that Quartus only supports synthesizeable VHDL and wait is > not synthesizeable. If I not mistake, you have only the waveform program > to create testbenches, and so I use Modelsim for my simulations of > Altera-targeted designs. > > Salman > > Pratip Mukherjee wrote: > > Is it possible to write a test bench using VHDL in Quartus? When I tried I > > got an error message telling me that wait <n> construct is not supported. > > Is that true or am I making some mistake? Is there any way, may be using > > tcl, I can simulate a VHDL like test bench? Testbench using waveforms just > > does not work for me. > > Thanks. > > > > Pratip Mukherjee > > pratipm.remove_this@hotmail.com-- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●June 4, 20042004-06-04
rickman <spamgoeshere4@yahoo.com> wrote in message news:<40BF8B40.A64DB0AF@yahoo.com>...> There is something missing in this discussion. If you are talking about > testbenches, then Quartus can't help you since testbenches are used in > simulations and Quartus is not a VHDL simulator. > > I agree that using waveforms to simulate FPGA designs is not desirable.I'd love to hear why. <...> Regards, -rajeev-
Reply by ●June 4, 20042004-06-04
Rajeev wrote:> > rickman <spamgoeshere4@yahoo.com> wrote in message news:<40BF8B40.A64DB0AF@yahoo.com>... > > There is something missing in this discussion. If you are talking about > > testbenches, then Quartus can't help you since testbenches are used in > > simulations and Quartus is not a VHDL simulator. > > > > I agree that using waveforms to simulate FPGA designs is not desirable. > > I'd love to hear why.A test bench is not just a static waveform generator, it can be an interactive environment simulator. I can write code to model an external memory or MCU bus cycles or any other interface. As my design progresses it can take a lot less work to keep a testbench up to date than it would to redo waveforms. Maybe it is just a personal preference, but I find a VHDL testbench to be the best way of testing a design I have found. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
Reply by ●June 5, 20042004-06-05
rickman <spamgoeshere4@yahoo.com> wrote in news:40C0DF60.2BF1AA9A@yahoo.com:> Rajeev wrote: >> >> rickman <spamgoeshere4@yahoo.com> wrote in message >> news:<40BF8B40.A64DB0AF@yahoo.com>... >> > There is something missing in this discussion. If you are talking >> > about testbenches, then Quartus can't help you since testbenches >> > are used in simulations and Quartus is not a VHDL simulator. >> > >> > I agree that using waveforms to simulate FPGA designs is not >> > desirable. >> >> I'd love to hear why. > > A test bench is not just a static waveform generator, it can be an > interactive environment simulator. I can write code to model an > external memory or MCU bus cycles or any other interface. As my > design progresses it can take a lot less work to keep a testbench up > to date than it would to redo waveforms. > > Maybe it is just a personal preference, but I find a VHDL testbench to > be the best way of testing a design I have found. >If the design has some Altera specific MegaFunction, then don't you have to have another version of the same file using generic VHDL construct? Can Xilinx/ModelSim be made to understand Altera specific constructs? I am talking about the free version of ModelSim which comes with WebPack. Thanks.
Reply by ●June 5, 20042004-06-05
Pratip Mukherjee wrote:> > rickman <spamgoeshere4@yahoo.com> wrote in > news:40C0DF60.2BF1AA9A@yahoo.com: > > A test bench is not just a static waveform generator, it can be an > > interactive environment simulator. I can write code to model an > > external memory or MCU bus cycles or any other interface. As my > > design progresses it can take a lot less work to keep a testbench up > > to date than it would to redo waveforms. > > > > Maybe it is just a personal preference, but I find a VHDL testbench to > > be the best way of testing a design I have found. > > > > If the design has some Altera specific MegaFunction, then don't you have > to have another version of the same file using generic VHDL construct? > Can Xilinx/ModelSim be made to understand Altera specific constructs? I > am talking about the free version of ModelSim which comes with WebPack. > Thanks.What MegaFunction are you thinking that I would use? I have found that the block rams can be described in generic VHDL. I expect that any other feature would be device specific. One that I will likely end up using is the cascade chain in the Altera parts, they are useful in wide input muxes. I believe I asked about how to get these from generic code and did not get a good answer from Altera. So I may have to do as you are saying and use a conditional depending on the target. I started to do that with the memory before I found that both environments worked well with generic code. Its not hard to do. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
