Using Altera libraries for Nios Dev Board

Hi,

I'm currently working on a project at my university for testing and
developing rate based protocols and I've been having some problems
with my dev board. I've been using the Altera Nios proffesional dev
board (with stratix FPGA). So far I've ran tests with UDP (over 2 dev
boards) to test the utilization of my network, which is 100 Mbps and I
keep getting numbers just under 10 Mbps. I've done tests on the lines
over PC's and they achieve over 40 so I know the line is not the
problem. The only thing I can see is that maybe the Ethernet/PHY chip
they use defaults to 10 Mbps, even though it says it auto detects to
100 or 10.

I was wondering if anyone has experience with the low level libraries,
like lan91c111.c, and could point me in the right direction. I would
be satisfied to just get a printout of the register status to see if
it is acutally setting itself to 10 Mbps. I've tried to use
nr_lan91c111_dump_registers() but it won't give me a printout of the
register banks. The lack of documentation also doesn't really help.
Any help would be great.

Thanks, Justin.

>problem. The only thing I can see is that maybe the Ethernet/PHY chip
>they use defaults to 10 Mbps, even though it says it auto detects to
>100 or 10.

Plug both lines into a switch/hub and look at the lights to find
out what speed the link is running at.

Put a scope on the wire... (or one of the wires going to the PHY
chip)

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jolivier@ee.umanitoba.ca (Justin) wrote in message news:<5d865b7e.0406150715.2a8c399b@posting.google.com>...
> Hi,
> 
> I'm currently working on a project at my university for testing and
> developing rate based protocols and I've been having some problems
> with my dev board. I've been using the Altera Nios proffesional dev
> board (with stratix FPGA). So far I've ran tests with UDP (over 2 dev
> boards) to test the utilization of my network, which is 100 Mbps and I
> keep getting numbers just under 10 Mbps. I've done tests on the lines
> over PC's and they achieve over 40 so I know the line is not the
> problem. The only thing I can see is that maybe the Ethernet/PHY chip
> they use defaults to 10 Mbps, even though it says it auto detects to
> 100 or 10.
> 
> I was wondering if anyone has experience with the low level libraries,
> like lan91c111.c, and could point me in the right direction. I would
> be satisfied to just get a printout of the register status to see if
> it is acutally setting itself to 10 Mbps. I've tried to use
> nr_lan91c111_dump_registers() but it won't give me a printout of the
> register banks. The lack of documentation also doesn't really help.
> Any help would be great.
> 
> Thanks, Justin.

Hi Justin,

In addition to what Hal posted about just checking the link speed (and
yes, all the C code that handles how the MAC/PHY are reset is in the
91c111 driver), I am curious what your software looks like that is
sending Ethernet data? The reason is that the 91c111 *should* boot up
and auto-negotiate to the highest speed available. On the other hand,
the typical bottleneck when doing embedded etherent communications is
with the CPU & protocol stack assembling packets to send.

Example: If you're running Nios at typical clock speeds and are
sending UDP data via the plugs stack, it would not surprise me at all
if the throughput was around 10Mbit. This can be accelerated quite
nicely through some simple HW acceleration (checksum & DMA use up most
of the CPU time). So, if the link speed is not the cause of your
problems, feel free to send me an email and I can send back an article
on this subject and some examples.

Jesse Kempa
Altera Corp.
jkempa at altera dot com