Is there a verilog version of PicoBlaze?

On 18 Jun 2004 02:43:41 -0700, henk@mediatronix.com (Henk van Kampen)
wrote:

>Dear Steve/Allan:
>What would be needed in my Picoblaze IDE to support Verilog. Please
>let me know, so when I find the time I can add that.

Hi Henk, it just needs to be able to generate the file containing the
ROM contents in Verilog instead of VHDL.
Kcpsm3 generates files in both languages, perhaps you could study what
it does.

This doesn't help the OP though, as the core itself is written in
VHDL.  Steve, would there be any problem if a third party (e.g. me)
were to publish a behavioural Verilog description of picoblaze[123]?

Regards,
Allan.

Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<f8f5d09c1bhectj9dm3qtv1e771tnug1j7@4ax.com>...
> This doesn't help the OP though, as the core itself is written in
> VHDL.  Steve, would there be any problem if a third party (e.g. me)
> were to publish a behavioural Verilog description of picoblaze[123]?

Allan:
The Picoblaze cores are, although VHDL, just instantiations of LUTS
and FF's. So a straight translation should be possible.
Henk

On 18 Jun 2004 14:33:28 -0700, henk@mediatronix.com (Henk van Kampen)
wrote:

>Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<f8f5d09c1bhectj9dm3qtv1e771tnug1j7@4ax.com>...
>> This doesn't help the OP though, as the core itself is written in
>> VHDL.  Steve, would there be any problem if a third party (e.g. me)
>> were to publish a behavioural Verilog description of picoblaze[123]?
>
>Allan:
>The Picoblaze cores are, although VHDL, just instantiations of LUTS
>and FF's. So a straight translation should be possible.

Possible, yes, but would it be frowned upon by Xilinx?

Regards,
Allan.

Allan Herriman wrote:

> On 18 Jun 2004 14:33:28 -0700, henk@mediatronix.com (Henk van Kampen)
> wrote:
> 
>>Allan:
>>The Picoblaze cores are, although VHDL, just instantiations of LUTS
>>and FF's. So a straight translation should be possible.
> 
> 
> Possible, yes, but would it be frowned upon by Xilinx?


I am not the official word of Xilinx but if you are buying Xilinx 
devices to use that code in, I doubt you will have a problem with this. 
   If you are trying to re-target this code to another vendor's FPGA, 
then you might.  The code was written to sell Xilinx FPGAs and as long 
as it does that in either VHDL or Verilog form, then I would not worry 
to much about the translation.  My suggestion however is to just 
synthesize your design with the processor defined as a black-box in you 
Verilog code and use the provided NGC file.  If you want to run a 
behavioral Verilog sim using it, then you can translate the NGC file to 
a structural UNISIM-based model using NGC2HDL.  Since it sounds like the 
original is structural, this should be practically the same thing as the 
VHDL version.  I would not suggest implementing the Verilog file 
produced by NGC2HDL however as it is only really intended to be used for 
simulation so I would stick with the original NGC file for 
implementation to be safe.

-- Brian


> 
> Regards,
> Allan.

I haven't used picoblaze, so take my comment accordingly:  If picoblaze is placed in the source code using generates, it may not be
possible to do it in verilog and retain the placement as well as the parameterization.  If using synplify, you can compile the VHDL with
the mapped output to verilog turned on to get a structural verilog model that you can use for simulation.  Be aware that SRL16's may not
be initialized properly though (I don't know if Synplicity fixed that bug in 7.5.1).

Allan Herriman wrote:

> On 18 Jun 2004 14:33:28 -0700, henk@mediatronix.com (Henk van Kampen)
> wrote:
>
> >Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<f8f5d09c1bhectj9dm3qtv1e771tnug1j7@4ax.com>...
> >> This doesn't help the OP though, as the core itself is written in
> >> VHDL.  Steve, would there be any problem if a third party (e.g. me)
> >> were to publish a behavioural Verilog description of picoblaze[123]?
> >
> >Allan:
> >The Picoblaze cores are, although VHDL, just instantiations of LUTS
> >and FF's. So a straight translation should be possible.
>
> Possible, yes, but would it be frowned upon by Xilinx?
>
> Regards,
> Allan.

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