Clock Phase Fun on Cyclone III

I've got a project going on a Cyclone III, and have hit an issue that 
seems like it has a simple solution if only I already knew it.

I've got a 125 MHz input clock (CLK125).  I've got an ADC that takes in 
an LVDS 250 MHz clock (CLKOUT), and outputs 250 Msps parallel LVDS data, 
changing on the rising edge of a regenerated 250 MHz clock (CLKFB).

The phase relationship of my FPGA to anything other than the ADC doesn't 
matter.  Jitter on CLKOUT isn't the femtosecond sensitivities than you 
might expect for a 250 Msps ADC; the application turns out not mind a 
bit of spectral smear.

So my goals are to generate from a 125 MHz reference:
* A 250 MHz clock going out to the ADC

* An internal 250 MHz clock; properly phase aligned to latch the ADC 
data in the center of the valid window.

* An internal 125 MHz clock for processing that can't be done at 250 
MHz, phase aligned to the internal 125 MHz

This seems like it should be pretty straightforward, that there's some 
obvious application of the PLL's source synchronous mode that makes this 
all just work, but I'm not seeing it.  I suppose I could use one PLL to 
turn CLK125 into CLKOUT, then source the second PLL from CLKFB, but that 
seems like it's going to leave me with an internal clock that's the 
result of cascading PLLs, and at 250 MHz that seems like the jitter 
might seriously cut into my timing margins.  Anyone have any thoughts?

Thanks,
Rob

-- 
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order.  See above to fix.

On Oct 26, 12:44=A0pm, Rob Gaddi <rga...@technologyhighland.invalid>
wrote:

>
> * An internal 125 MHz clock for processing that can't be done at 250
> MHz, phase aligned to the internal 125 MHz
>
> This seems like it should be pretty straightforward, that there's some
> obvious application of the PLL's source synchronous mode that makes this
> all just work, but I'm not seeing it. =A0I suppose I could use one PLL to
> turn CLK125 into CLKOUT, then source the second PLL from CLKFB, but that
> seems like it's going to leave me with an internal clock that's the
> result of cascading PLLs, and at 250 MHz that seems like the jitter
> might seriously cut into my timing margins. =A0Anyone have any thoughts?
>

Why not just bring the ADC data into a dual clock FIFO clocked on one
side by CLKFB?  You may also be able to widen the data prior to
putting it into the FIFO so that the output side can be clocked by
CLK125.

KJ