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Xilinx CPLD XC95144 for Driving Sigma Delta DAC

Started by nba83 September 23, 2012
hi
i would like to drive a Digital to analog converter(AD1933) with a cpld,
here is what i'm trying to do: i have a micro controller that generate
25Mbps DAC data but is not capable of driving the DAC through high speed
SPI(i need over 35MHz spi interface), so i decided to drive the dac with
cpld or fpga,
since i don't want to increase project cost by using fpga so i prefer to
use cpld XC95XX(XC95144) for this application, i'm not sure if this cpld is
capable of driving the dac at this rate, any one have any idea about the
feasibility of this plan??
tnx in advance for help
	   
					
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Posted through http://www.FPGARelated.com
On Sun, 23 Sep 2012 00:57:27 -0500, nba83 wrote:

> hi i would like to drive a Digital to analog converter(AD1933) with a > cpld, here is what i'm trying to do: i have a micro controller that > generate 25Mbps DAC data but is not capable of driving the DAC through > high speed SPI(i need over 35MHz spi interface), so i decided to drive > the dac with cpld or fpga, > since i don't want to increase project cost by using fpga so i prefer to > use cpld XC95XX(XC95144) for this application, i'm not sure if this cpld > is capable of driving the dac at this rate, any one have any idea about > the feasibility of this plan?? > tnx in advance for help
How are you going to get data into your CPLD at that rate? Parallel? Some other serial interface that also needs to run at 35MHz or more? Your feasibility may break up on other rocks than whether the CPLD is up to it. Having said that -- to my beginner's eyes a parallel in, serial out, 35MHz SPI should be doable with a part like that. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.com
On 9/23/2012 1:57 AM, nba83 wrote:
> hi > i would like to drive a Digital to analog converter(AD1933) with a cpld, > here is what i'm trying to do: i have a micro controller that generate > 25Mbps DAC data but is not capable of driving the DAC through high speed > SPI(i need over 35MHz spi interface), so i decided to drive the dac with > cpld or fpga, > since i don't want to increase project cost by using fpga so i prefer to > use cpld XC95XX(XC95144) for this application, i'm not sure if this cpld is > capable of driving the dac at this rate, any one have any idea about the > feasibility of this plan?? > tnx in advance for help
Without looking at the data sheet, I am pretty sure these parts can drive a 35 MHz serial shift register. 35 MHz is pretty slow for any programmable logic part. How will the CPLD talk to the micro? I assume you plan to use a parallel, memory mapped interface? Can your MCU keep up with the data speed? Rick
On 9/23/2012 4:27 PM, rickman wrote:
> On 9/23/2012 1:57 AM, nba83 wrote: >> hi >> i would like to drive a Digital to analog converter(AD1933) with a cpld, >> here is what i'm trying to do: i have a micro controller that generate >> 25Mbps DAC data but is not capable of driving the DAC through high speed >> SPI(i need over 35MHz spi interface), so i decided to drive the dac with >> cpld or fpga, >> since i don't want to increase project cost by using fpga so i prefer to >> use cpld XC95XX(XC95144) for this application, i'm not sure if this >> cpld is >> capable of driving the dac at this rate, any one have any idea about the >> feasibility of this plan?? >> tnx in advance for help > > Without looking at the data sheet, I am pretty sure these parts can > drive a 35 MHz serial shift register. 35 MHz is pretty slow for any > programmable logic part. > > How will the CPLD talk to the micro? I assume you plan to use a > parallel, memory mapped interface? Can your MCU keep up with the data > speed? > > Rick
BTW, there are some very low cost FPGAs available, around $3. Check out the Lattice ice40 series. Rick
"nba83" <3224@embeddedrelated> wrote:

>hi >i would like to drive a Digital to analog converter(AD1933) with a cpld, >here is what i'm trying to do: i have a micro controller that generate >25Mbps DAC data but is not capable of driving the DAC through high speed >SPI(i need over 35MHz spi interface), so i decided to drive the dac with >cpld or fpga, >since i don't want to increase project cost by using fpga so i prefer to >use cpld XC95XX(XC95144) for this application, i'm not sure if this cpld is >capable of driving the dac at this rate, any one have any idea about the >feasibility of this plan??
It shouldn't be a problem. I use these CPLDs for rescaling VGA resolution TFT displays at reduced color depths. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------
> >How are you going to get data into your CPLD at that rate? Parallel? >Some other serial interface that also needs to run at 35MHz or more? > >Your feasibility may break up on other rocks than whether the CPLD is up >to it. > >Having said that -- to my beginner's eyes a parallel in, serial out, >35MHz SPI should be doable with a part like that. > >-- >Tim Wescott >Control system and signal processing consulting >www.wescottdesign.com >
I want to feed data in parallel (8bit) to CPLD, buffer it for about 100 bytes, and then start to drive SPI Out. I am some how concerned about the speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it is -10C(means 10nsec delay for IO routs), does this delay impose any problem? Since I want to drive the CPLD with 100MHZ oscillator clk input, and by clk dividing generate a 50 or 40MHz clk for SPI. tnx for any helpful comments :) --------------------------------------- Posted through http://www.FPGARelated.com
On 09/24/2012 08:09 AM, nba83 wrote:

> I want to feed data in parallel (8bit) to CPLD, buffer it for about 100 > bytes, and then start to drive SPI Out. I am some how concerned about the > speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it is > -10C(means 10nsec delay for IO routs), does this delay impose any problem? > Since I want to drive the CPLD with 100MHZ oscillator clk input, and by clk > dividing generate a 50 or 40MHz clk for SPI. > tnx for any helpful comments :)
The problem isn't going to be the speed, but where the CPLD is going to store the 100 bytes. The XC95144XL only has 144 bits of storage total.
>On 09/24/2012 08:09 AM, nba83 wrote: > >> I want to feed data in parallel (8bit) to CPLD, buffer it for about 100 >> bytes, and then start to drive SPI Out. I am some how concerned about
the
>> speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it is >> -10C(means 10nsec delay for IO routs), does this delay impose any
problem?
>> Since I want to drive the CPLD with 100MHZ oscillator clk input, and by
clk
>> dividing generate a 50 or 40MHz clk for SPI. >> tnx for any helpful comments :) > >The problem isn't going to be the speed, but where the CPLD is going to >store the 100 bytes. The XC95144XL only has 144 bits of storage total. > >
I have implemented a 1k byte dual port ram in this cpld logic in xilinx ise, but i havn't tested it yet. I have not added the DAC driver to it yet, i'm not sure if this cpld is enough for these modules. here is the implementation for RAM: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dpram_4x2045 is Port ( DIN : in std_logic_vector(7 downto 0); RE_ADDRESS : in std_logic_vector(10 downto 0); wr_address :in std_logic_vector(10 downto 0); CLCK_wr : in std_logic; CLCK_re : in std_logic; We : in std_logic; Re : in std_logic; dout : out std_logic_vector(7 downto 0)); end dpram_4x2045 ; architecture Behavioral of dpram_4x2045 is type my_data is array (0 to 2048)of std_logic_vector(7 downto 0) ; signal rom: my_data; begin process (clck_wr)--write begin if (clck_wr'event and clck_wr = '0') then if (we = '1') then rom(conv_integer(WR_address)) <= din; end if; end if; end process; process (clck_re)--read begin if (clck_re'event and clck_re = '1') then ---e if (Re = '1') then dout<=rom(conv_integer(RE_address)); end if; end if; end process; end Behavioral; and the other module will receive bytes from parallel port and write it in buffer, after writing 100 bytes, spi out module is enabled. and send out data bytes --------------------------------------- Posted through http://www.FPGARelated.com
On Mon, 24 Sep 2012 06:00:15 -0500
"nba83" <3224@embeddedrelated> wrote:

> >On 09/24/2012 08:09 AM, nba83 wrote: > > > >> I want to feed data in parallel (8bit) to CPLD, buffer it for about 100 > >> bytes, and then start to drive SPI Out. I am some how concerned about > the > >> speed grade of the CPLD I intend to use(XC95144XL-TQG144-10C), it is > >> -10C(means 10nsec delay for IO routs), does this delay impose any > problem? > >> Since I want to drive the CPLD with 100MHZ oscillator clk input, and by > clk > >> dividing generate a 50 or 40MHz clk for SPI. > >> tnx for any helpful comments :) > > > >The problem isn't going to be the speed, but where the CPLD is going to > >store the 100 bytes. The XC95144XL only has 144 bits of storage total. > > > > > > I have implemented a 1k byte dual port ram in this cpld logic in xilinx > ise, but i havn't tested it yet. I have not added the DAC driver to it yet, > i'm not sure if this cpld is enough for these modules. here is the > implementation for RAM: >
You've written behavioral VHDL that describes a dual-port block RAM. That's lovely and all, but have you checked the CPLD datasheet and confirmed that there is a block RAM resource on the chip that will do that? You could also write VHDL describing a unicorn, but you'd be hard pressed to make it pass synthesis. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.
nba83 wrote:

> hi > i would like to drive a Digital to analog converter(AD1933) with a cpld, > here is what i'm trying to do: i have a micro controller that generate > 25Mbps DAC data but is not capable of driving the DAC through high speed > SPI(i need over 35MHz spi interface), so i decided to drive the dac with > cpld or fpga, > since i don't want to increase project cost by using fpga so i prefer to > use cpld XC95XX(XC95144) for this application, i'm not sure if this cpld > is capable of driving the dac at this rate, any one have any idea about > the feasibility of this plan??
The 9500XL series starts out very cheap, but the larger components, like the 95144, start to get expensive. You can check the prices of the CoolRunner series (XCR), also quite cheap even in the larger sizes. But, you are talking about significant amounts of registers, and the CPLDs are very short on them. Block RAMs don't exist at all on Xilinx CPLDs, and probably not on anybody else's, either. The smaller Spartan 3A are quite inexpensive, but need a download serial PROM. SST's 25VF010A will load the XC3S50A FPGA with no additional chips, and is under $1 in small quantity. You can get the Spartan 3AN version of the FPGA with built-in SPROM, but it costs more than the separate solution. You do need to find a way to program the SST SPROM, but it is fairly easy to do. Totally minimal hardware, and pretty simple software. Jon