On 7/30/2013 10:25 PM, Gabor wrote:> On 7/30/2013 9:03 PM, Rob Doyle wrote: >> On 7/30/2013 11:37 AM, rickman wrote: >>> Spartan 6 parts give a *lot* more functionality, but I'd have to use >>> a 256 pin 1.0 mm BGA *and* external flash *and* the 1.2 volt supply >>> *and* they are twice the price. Maybe I'll talk to the disties. >>> Maybe they can do something about the price at least. >> >> The smaller Spartan 6 parts do come in a 144 pin TQFP package. Too small? >> >> Rob. > > Apparently the 144 TQ package is too big (physically). And once you > look at a 256-ball 1mm BGA you could find any number of devices > including those from Lattice (XP2?). For internals, the smallest > Spartan 6 is about the size of the original XP part he was using. > > As to price, we never pay anything near list for Xilinx parts, but > we don't get the same steep discount on Spartan 6 as we do on other > series.There is some irony, the parts the smallest Spartan 6 comes in are *too* small in terms of ball pitch. They require PCB design rules down to 3/3 trace/space. To get a FTG256 BGA you have to bump up to the next size which is some four times bigger than the part I'm using now. It has nearly 6K LUTs and they are 6 input LUTs rather than 4 input. It also has tons of multipliers and RAM, so it is a *lot* more device. The Digikey price is about double too..., but that can be negotiable. -- Rick
Lattice Announces EOL for XP and EC/P Product Lines
Started by ●July 30, 2013
Reply by ●July 31, 20132013-07-31
Reply by ●July 31, 20132013-07-31
On 7/30/2013 2:37 PM, rickman wrote:> > I have yet to check out the Altera line. I don't remember them having > anything I liked in a nice package. But that will be something to do > later today. I guess I should check out the Micro-Semi line as well. > It's been a while since I looked hard at their parts and, oh yeah, there > is the PSOC from Cypress. I don't think that was an option at the time I > did this design.I went to the Cypress web site and I can't find a data sheet on their PSOC parts. They also encrypt the info on the broad classes of devices behind marketing speak. So I can't even get a feel for what they are capable of. -- Rick
Reply by ●July 31, 20132013-07-31
rickman wrote:> On 7/30/2013 9:50 PM, Jon Elson wrote: >> rickman wrote: >> >>> >> The smallest Spartan 3A is under $10, the 3AN is about $15. >> >>> Actually my main concern with the external flash is the whole JTAG >>> programming at the factory and/or lab thing, but there are likely many >>> ways to deal with that including having them programmed before assembly. >>> It is just that I've been using these Flash FPGAs for some time now >>> and I'm very used to them. >>> >> The 3AN can be programmed by JTAG, the SST serial EPROM I use on >> the 3A is not JTAG, although a flexible programmer or tester >> could easily be "taught" the protocol. I chose this device >> so I could have field-replaceable firmware. I had to make an >> SO-8 to DIP converter board though, as the SST chip is only >> available in a couple SMT packages. > > Yeah, I am supposed to provide JTAG programmability through the > equipment this daughtercard is plugged into. That is, I provide the > JTAG port, it is up to them to do the software to program it. That is > one of my concerns with an external seral prom. May not be easy to do > in an 8 pin package... But if they can learn the protocol, maybe that > would work too. We'll see. After 5 years we still have not required > this functionality. But I'll be pushing for increased capability in the > new version to allow it to be sold into new areas. So remote updates > may be more important then. >Most recent parts from Xilinx including Spartan 3A have SPI master mode configuration, requiring nothing extra over the SPI flash itself and a handful of resistors. Indirect SPI flash programming over JTAG is supported by Impact, and you can generate SVF files to do the programming with an embedded processor. Also because the pins used for SPI config become I/O after config, you can use the SPI flash in your design, and possibly come up with a more "native" solution to field updates (without using JTAG). -- Gabor
Reply by ●July 31, 20132013-07-31
On 7/31/2013 5:13 PM, GaborSzakacs wrote:> > Most recent parts from Xilinx including Spartan 3A have SPI master > mode configuration, requiring nothing extra over the SPI flash itself > and a handful of resistors. Indirect SPI flash programming over > JTAG is supported by Impact, and you can generate SVF files to > do the programming with an embedded processor. Also because the > pins used for SPI config become I/O after config, you can use > the SPI flash in your design, and possibly come up with a more > "native" solution to field updates (without using JTAG).I'm not sure what the use of Impact implies. Does that mean connecting a PC with a dongle cable? That would be used in the factory perhaps, but in the field they want to use an CPU to drive the JTAG signals. They have that working for an Altera part, but not yet for the Lattice part and of course not for any Xilinx parts. -- Rick
Reply by ●July 31, 20132013-07-31
rickman wrote:> I'm not sure what the use of Impact implies. Does that mean connecting > a PC with a dongle cable? That would be used in the factory perhaps, > but in the field they want to use an CPU to drive the JTAG signals. > They have that working for an Altera part, but not yet for the Lattice > part and of course not for any Xilinx parts. >Yes, you certainly can do that, and Xilinx has some articles on how to write your computer code to take a .bit file loaded into a processor's EPROM and perform the various modes of download available. There is serial config, parallel config, JTAG config, etc. To do this from a CPU, you want slave mode, where the CPU clocks the bits into the FPGA. For a serial EPROM chip you select master serial, so the FPGA generates the bit clock. The newer FPGAs have almost too MANY modes of configuration. Jon
Reply by ●July 31, 20132013-07-31
Rick... I check the Actel/Microsemi lead you started down on the original p= ost, they have options available in your target size, 100 pin QFP, are flas= h based/reprogrammable over JTAG and I think should have very similar power= requirements to your original design. I am looking at this chip, availabl= e today on digikey: AGL250V2-VQG100, 14 mm2, $25.40, 68 I/O and a fair amou= nt of logic. If you don't need that much logic and want a cheaper part the= y go down from there in the same package.
Reply by ●August 1, 20132013-08-01
kl. 00:54:41 UTC+2 wednesday 31. july 2013 rickman wrote:> In fact, I'm skipping Altera for the moment and skipping over to=20 > MicroSemi and Cypress to see if their combination CPU/Logic devices=20 > might do the job well and let me eliminate the stereo CODEC to (another==20> part that could go obsolete at any time). I seem to recall that the=20 > Cypress part might be just the ticket but the MicroSemi part runs some=20 > $50 at the low point. The current Lattice part is running under $10.We've got a quote for the Microsemi SF2 M2S010 (without T) somewhere in the= middle of that price difference in low volume. The features of SF2 somehow= justified the additional price because we could avoid a separate flash and= MCU externally. The flexibility in configuration of the FPGA and MSS and h= ard preipherals also give us design freedom. Low power consumption was defi= nitively something worth a bit extra. --=20 Svenn
Reply by ●August 2, 20132013-08-02
On 8/1/2013 3:21 AM, Svenn Are Bjerkem wrote:> kl. 00:54:41 UTC+2 wednesday 31. july 2013 rickman wrote: >> In fact, I'm skipping Altera for the moment and skipping over to >> MicroSemi and Cypress to see if their combination CPU/Logic devices >> might do the job well and let me eliminate the stereo CODEC to (another >> part that could go obsolete at any time). I seem to recall that the >> Cypress part might be just the ticket but the MicroSemi part runs some >> $50 at the low point. The current Lattice part is running under $10. > > We've got a quote for the Microsemi SF2 M2S010 (without T) somewhere in the middle of that price difference in low volume. The features of SF2 somehow justified the additional price because we could avoid a separate flash and MCU externally. The flexibility in configuration of the FPGA and MSS and hard preipherals also give us design freedom. Low power consumption was definitively something worth a bit extra.Yes, each project has its own requirements so some will justify a higher price for the improved integration. I am not so familiar with the Microsemi part and I not had time to dig into their offerings. I don't even know if they have anything new in the last year or two. The main stumbling block for the Cypress part is the lack of CD quality CODEC I believe. But that is only a $3 part at most. There are also some op amps on the board which I doubt can be replaced since at least four of them are used to drive a 12 volt supply into a 50 ohm load (8 Vp-p IIRC). The remaining parts are analog switches on the analog I/O, analog switches on the digital I/O to act as 5-3 volt level converters and a two channel RS-422 input/output chip. I doubt any of this can be pulled into the Microsemi part leaving us with this possibly replacing the existing FPGA and the CODEC at best. So it would be hard to justify replacing what is otherwise $15 worth of parts with a $30 part if I read your post correctly. By low volume I assume you mean qty 100 ball park. Funny about Cypress. I seem to recall their web site having gone downhill over the last few years. When I tried to download a data sheet on their parts I couldn't find one! They have links for their software and for samples, but none for a data sheet!!!? Maybe it is embedded in their development software? They also give a crappy overview of their parts. So far I haven't figured it out but I guess it is worth a second try. -- Rick
Reply by ●August 2, 20132013-08-02
On 7/31/2013 6:23 PM, Jon Elson wrote:> rickman wrote: > > >> I'm not sure what the use of Impact implies. Does that mean connecting >> a PC with a dongle cable? That would be used in the factory perhaps, >> but in the field they want to use an CPU to drive the JTAG signals. >> They have that working for an Altera part, but not yet for the Lattice >> part and of course not for any Xilinx parts. >> > Yes, you certainly can do that, and Xilinx has some articles > on how to write your computer code to take a .bit file loaded into > a processor's EPROM and perform the various modes of download > available. There is serial config, parallel config, JTAG config, > etc. To do this from a CPU, you want slave mode, where the > CPU clocks the bits into the FPGA. For a serial EPROM chip you > select master serial, so the FPGA generates the bit clock. > The newer FPGAs have almost too MANY modes of configuration.I think what you are describing is rather different. This is the slave serial config mode which is somewhat limited in functionality. The interface my customer has provided is intended to use a JTAG interface. In the case of the serial EEPROM the CPU would either program the EEPROM directly or drive the JTAG on the FPGA to program the EEPROM. I'm pretty sure the customer does *not* want to load the part every time it is booted, just once in a programming mode, then the board loads itself when it boots up. I'm not sure if this is what you were describing or not. -- Rick
Reply by ●August 2, 20132013-08-02
