ISE: use verilog-modules in an vhdl-design-flow

Hallo,
this may be an typical newbie-question(sorry).

My project is described in vhdl, but i have an working component in verilog
i want to use within.
How will i get the component in my project ?


thanks for any answer

Thomas Oehme

On Fri, 5 Sep 2003 09:39:39 +0200, "Thomas Oehme" <toehme@freenet.de>
wrote:

>Hallo,
>this may be an typical newbie-question(sorry).
>
>My project is described in vhdl, but i have an working component in verilog
>i want to use within.
>How will i get the component in my project ?
>
>
>thanks for any answer
>
>Thomas Oehme

In ISE 5.x, you can only use one of VHDL and Verilog at a time, using
the normal "flow".

Workarounds:

1.  Use a compiler such as Synplify or Leonardo.

2a. Rewrite your Verilog in VHDL.
2b. Rewrite your VHDL in Verilog.

3.  Wait until ISE 6.1 (coming RSN), which supposedly will support
VHDL and Verilog at the same time.

4.  Compile your Verilog to EDIF (or whatever) as a separate step, and
instantiate that in your VHDL as a black box.  Compile your VHDL
*without* the Verilog module as part of the list of files to compile.
The back end tools (ngdbuild) will patch the already compiled Verilog
module into the hole left in the VHDL.
Note that this will require two "projects."

Regards,
Allan.

Thomas Oehme <toehme@freenet.de> wrote in message
news:bj9egd$gmu21$1@ID-205636.news.uni-berlin.de...
> Hallo,
> this may be an typical newbie-question(sorry).
> My project is described in vhdl, but i have an working component in
verilog
> i want to use within.
> How will i get the component in my project ?
> thanks for any answer
> Thomas Oehme

Thomas,

This depends on your tool set.

If you've got HDL->third party synthesis tool->FPGA P+R tool, this
should be easy enough.

An overview is....
Instantiate a VHDL component that has the same port mapping as
the VHDL component. Synthesise your VHDL and a black box is
created in the EDIF file for the component.

Synthesise the verilog to create the component that'll fit in the
black box (make sure you don't allow output buffers to be
implelmented).

Run your P+R tool, it should then plug the edif of the component
into the VHDL file.


Nial Stewart

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk

Hi Allan:

you should be able to black box the thing, and use it as a lib

Andrew

Allan Herriman wrote:

>On Fri, 5 Sep 2003 09:39:39 +0200, "Thomas Oehme" <toehme@freenet.de>
>wrote:
>
>  
>
>>Hallo,
>>this may be an typical newbie-question(sorry).
>>
>>My project is described in vhdl, but i have an working component in verilog
>>i want to use within.
>>How will i get the component in my project ?
>>
>>
>>thanks for any answer
>>
>>Thomas Oehme
>>    
>>
>
>In ISE 5.x, you can only use one of VHDL and Verilog at a time, using
>the normal "flow".
>
>Workarounds:
>
>1.  Use a compiler such as Synplify or Leonardo.
>
>2a. Rewrite your Verilog in VHDL.
>2b. Rewrite your VHDL in Verilog.
>
>3.  Wait until ISE 6.1 (coming RSN), which supposedly will support
>VHDL and Verilog at the same time.
>
>4.  Compile your Verilog to EDIF (or whatever) as a separate step, and
>instantiate that in your VHDL as a black box.  Compile your VHDL
>*without* the Verilog module as part of the list of files to compile.
>The back end tools (ngdbuild) will patch the already compiled Verilog
>module into the hole left in the VHDL.
>Note that this will require two "projects."
>
>Regards,
>Allan.
>  
>